Datasheet

  
  
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram, MSP430x20x3
Basic Clock
System+
RAM
128B
128B
Brownout
Protection
RST/NMI
VCC VSS
MCLK
SMCLK
Watchdog
WDT+
15/16−Bit
Timer_A2
2CC
Registers
16MHz
CPU
incl. 16
Registers
Emulation
(2BP)
XOUT
JTAG
Interface
Flash
2kB
1kB
ACLK
XIN
Port P1
8I/O
Interrupt
capability,
pull−up/down
resistors
SD16_A
16−bit
Sigma−
Delta A/D
Converter
P1.x & JTAG
8 2
Port P2
2 I/O
Interrupt
capability,
pull−up/down
resistors
MDB
MAB
USI
Universal
Serial
Interface
SPI, I2C
Spy−Bi Wire
P2.x &
XIN/XOUT
NOTE: See port schematics section for detailed I/O information.