Datasheet

  
  
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005
59
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P1 (P1.4 to P1.7) pin functions, MSP430x20x2
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
X
FUNCTION
P1DIR.x P1SEL.x USIP.x ADC10AE.x INCHx
JTAG
Mode
P1.4/SMCLK/A4/
VREF+/VeREF+/
4
P1.4† Input/Output 0/1 0 0 N/A 0
P1.4/SMCLK/A4/
VREF+/VeREF+/
TCK
4
N/A 0 1 0 N/A 0
TCK
SMCLK 1 1 0 N/A 0
A4 (see Note 3) X X
N/A
1 4 0
VREF+/VeREF+
(see Notes 3, 4)
X X
N/A
1 N/A 0
TCK (see Note 5) X X X X 1
P1.5/TA0/SCLK/A5/
TMS
5
P1.5† Input/Output 0/1 0 X 0 N/A 0
P1.5/TA0/SCLK/A5/
TMS
5
N/A 0 1 X 0 N/A 0
Timer_A2.TA0 1 1 X 0 N/A 0
SCLK X X 1 0 N/A 0
A5 (see Note 3) X X X 1 5 0
TMS (see Note 5) X X X X X 1
P1.6/TA1/SDO/SCL/A6/
TDI
6
P1.6† Input/Output 0/1 0 X 0 N/A 0
P1.6/TA1/SDO/SCL/A6/
TDI
6
Timer_A2.CCI1B 0 1 X 0 N/A 0
Timer_A2.TA1 1 1 X 0 N/A 0
SDO (SPI) / SCL (I2C) X X 1 0 N/A 0
A6 (see Note 3) X X X 1 6 0
TDI (see Note 5) X X X X X 1
P1.7/SDI/SDA/A7/
TDO/TDI
7
P1.7† Input/Output 0/1 0 X 0 N/A 0
P1.7/SDI/SDA/A7/
TDO/TDI
7
N/A 0 1 X 0 N/A 0
DVSS 1 1 X 0 N/A 0
SDI (SPI) / SDA (I2C) X X 1 0 N/A 0
A7 (see Note 3) X X X 1 7 0
TDO/TDI (see Notes 5,
6)
X X X X X 1
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the ADC10AE.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when
applying analog signals.
4. The reference voltage is output if bit REFOUT in register ADC10CTL0 is set. An applied voltage is used as positive reference if
bits SREF0/1 in register ADC10CTL0 are set to 10 or 11.
5. In JTAG mode the internal pull-up/down resistors are disabled.
6. Function controlled by JTAG