Datasheet

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005
58
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P1 (P1.3) pin schematics, MSP430x20x2
Bus
Keeper
EN
Direction
0: Input
1: Output
P1SEL.3
1
0
P1DIR.3
P1IN.3
P1IRQ.3
D
EN
Module X IN
1
0
Module X OUT
P1OUT.3
Interrupt
Edge
Select
Q
EN
Set
P1SEL.3
P1IES.3
P1IFG.3
P1IE.3
P1.3/ADC10CLK/
A3/VREF−/VeREF−
1
0
DVSS
DVCC
P1REN.3
ADC10AE.3
1
To ADC 10 V
Pad Logic
INCHx = 3
A3
R−
1
0
SREF2
VSS
Port P1 (P1.0 to P1.3) pin functions, MSP430x20x2
PIN NAME (P1.X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
X
FUNCTION
P1DIR.x P1SEL.x ADC10AE.x INCHx
P1.3/ADC10CLK/
A3/VREF−/VeREF−
3
P1.3† Input/Output 0/1 0 0 N/A
P1.3/ADC10CLK/
A3/VREF−/VeREF−
3
N/A 0 1 0 N/A
ADC10CLK 1 1 0 N/A
A3 (see Note 3) X X 1 3
VREF−/VeREF− (see Notes 3, 4) X X 1 N/A
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the ADC10AE.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when
applying analog signals.
4. An applied voltage is used as negative reference if bit SREF3 in register ADC10CTL0 is set.