Datasheet

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  
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005
53
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P1 (P1.7) pin schematics, MSP430x20x1
From JTAG
From JTAG (TDO)
Bus
Keeper
EN
Direction
0: Input
1: Output
P1SEL.7
1
0
P1DIR.7
P1IN.7
P1IRQ.7
D
EN
Module X IN
1
0
Module X OUT
P1OUT.7
Interrupt
Edge
Select
Q
EN
Set
P1SEL.7
P1IES.7
P1IFG.7
P1IE.7
P1.7/CAOUT/CA7/TDO/TDI
1
0
DVSS
DVCC
P1REN.7
To JTAG
From JTAG
1
CAPD.7
Pad Logic
From Comparator_A+
To Comparator_A+
Control signal “From Comparator_A+”
PIN NAME
FUNCTION
SIGNAL “FROM COMPARATOR_A+” = 1
PIN NAME
FUNCTION
P2CA3 P2CA2 P2CA1
P1.7/CAOUT/CA7/TDO/TDI CA7 1 1 1
NOTES: 1. N/A: Not available or not applicable.