Datasheet

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  
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005
50
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P1 (P1.0 to P1.3) pin schematics, MSP430x20x1
Bus
Keeper
EN
Direction
0: Input
1: Output
P1SEL.x
1
0
P1DIR.x
P1IN.x
P1IRQ.x
D
EN
Module X IN
1
0
Module X OUT
P1OUT.x
Interrupt
Edge
Select
Q
EN
Set
P1SEL.x
P1IES.x
P1IFG.x
P1IE.x
P1.0/TACLK/ACLK/CA0
P1.1/TA0/CA1
P1.2/TA1/CA2
P1.3/CAOUT/CA3
1
0
DVSS
DVCC
P1REN.x
CAPD.x
Pad Logic
From Comparator_A+
To Comparator_A+
1
Control signal “From Comparator_A+”
PIN NAME
FUNCTION
SIGNAL “FROM COMPARATOR_A+” = 1
PIN NAME
FUNCTION
P2CA4 P2CA0 P2CA3 P2CA2 P2CA1
P1.0/TACLK/ACLK/CA0
CA0 0 1 N/A N/A N/A
P1.1/TA0/CA1
CA1 1 0
OR
0 0 1
P1.2/TA1/CA2
CA2 1 1
OR
0 1 0
P1.3/CAOUT/CA3
CA3 N/A N/A 0 1 1
NOTES: 1. N/A: Not available or not applicable.