Datasheet

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
interrupt enable 1 and 2
7654 0
OFIE WDTIE
321
rw-0 rw-0 rw-0
Address
0h
NMIIEACCVIE
rw-0
WDTIE: Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer
is configured in interval timer mode.
OFIE: Oscillator fault enable
NMIIE: (Non)maskable interrupt enable
ACCVIE: Flash access violation interrupt enable
7654 0321
Address
01h
interrupt flag register 1 and 2
7654 0
OFIFG WDTIFG
321
rw-0 rw-1 rw-(0)
Address
02h NMIIFG
rw-(0)
RSTIFG
rw-(1)
PORIFG
WDTIFG: Set on Watchdog Timer overflow (in watchdog mode) or security key violation.
Reset on V
CC
power-up or a reset condition at RST/NMI pin in reset mode.
OFIFG: Flag set on oscillator fault
RSTIFG: External reset interrupt flag. Set on a reset condition at RST
/NMI pin in reset mode. Reset on V
CC
power-up
PORIFG: Power-On Reset interrupt flag. Set on V
CC
power-up.
NMIIFG: Set via RST
/NMI-pin
7654 0321
Address
03h
Legend rw:
rw-0,1:
Bit can be read and written.
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
rw-(0,1):
SFR bit is not present in device