Datasheet

  
  
SLAS272F − JULY 2000 − REVISED JUNE 2004
42
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic (continued)
port P2, P2.3 to P2.4, input/output with Schmitt-trigger
Bus Keeper
P2IN.3
P2OUT.3
Pad Logic
P2DIR.3
P2SEL.3
Module X OUT
Edge
Select
Interrupt
P2SEL.3
P2IES.3
P2IFG.3
P2IE.3P2IRQ.3
Direction Control
From Module
P2.3/CA0/TA1
0
1
0
1
Interrupt
Flag
Set
EN
Q
Module X IN
EN
D
P2IN.4
P2OUT.4
Pad Logic
P2DIR.4
P2SEL.4
Module X OUT
Edge
Select
Interrupt
P2SEL.4
P2IES.4
P2IFG.4
P2IE.4P2IRQ.4
Direction Control
From Module
P2.4/CA1/TA2
0
1
0
1
Interrupt
Flag
Set
EN
Q
Module X IN
EN
D
Comparator_A
−
+
Reference Block
CCI1B
CAF
CAREF
P2CA
CAEX
CAREF
Bus Keeper
CAPD.3
CAPD.4
To Timer_A3
0: Input
1: Output
0: Input
1: Output
PnSel.x PnDIR.x
DIRECTION
CONTROL
FROM MODULE
PnOUT.x MODULE X OUT PnIN.x MODULE X IN PnIE.x PnIFG.x PnIES.x
P2Sel.3 P2DIR.3 P2DIR.3 P2OUT.3 Out1 signal
†
P2IN.3 unused P2IE.3 P2IFG.3 P2IES.3
P2Sel.4 P2DIR.4 P2DIR.4 P2OUT.4 Out2 signal
†
P2IN.4 unused P2IE.4 P2IFG.4 P2IES.4
†
Signal from Timer_A