Datasheet

  
  
SLAS272F − JULY 2000 − REVISED JUNE 2004
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS
USART1
(MSP430x14x and
Transmit buffer U1TXBUF 07Fh
USART1
(MSP430x14x and
MSP430x14x1 only)
Receive buffer U1RXBUF 07Eh
MSP430x14x1 only)
Baud rate U1BR1 07Dh
Baud rate U1BR0 07Ch
Modulation control U1MCTL 07Bh
Receive control U1RCTL 07Ah
Transmit control U1TCTL 079h
USART control U1CTL 078h
USART0
Transmit buffer U0TXBUF 077h
USART0
Receive buffer U0RXBUF 076h
Baud rate U0BR1 075h
Baud rate U0BR0 074h
Modulation control U0MCTL 073h
Receive control U0RCTL 072h
Transmit control U0TCTL 071h
USART control U0CTL 070h
Comparator_A
Comparator_A port disable CAPD 05Bh
Comparator_A
Comparator_A control2 CACTL2 05Ah
Comparator_A control1 CACTL1 059h
Basic Clock
Basic clock system control2 BCSCTL2 058h
Basic Clock
Basic clock system control1 BCSCTL1 057h
DCO clock frequency control DCOCTL 056h
Port P6
Port P6 selection P6SEL 037h
Port P6
Port P6 direction P6DIR 036h
Port P6 output P6OUT 035h
Port P6 input P6IN 034h
Port P5
Port P5 selection P5SEL 033h
Port P5
Port P5 direction P5DIR 032h
Port P5 output P5OUT 031h
Port P5 input P5IN 030h
Port P4
Port P4 selection P4SEL 01Fh
Port P4
Port P4 direction P4DIR 01Eh
Port P4 output P4OUT 01Dh
Port P4 input P4IN 01Ch
Port P3
Port P3 selection P3SEL 01Bh
Port P3
Port P3 direction P3DIR 01Ah
Port P3 output P3OUT 019h
Port P3 input P3IN 018h
Port P2
Port P2 selection P2SEL 02Eh
Port P2
Port P2 interrupt enable P2IE 02Dh
Port P2 interrupt-edge select P2IES 02Ch
Port P2 interrupt flag P2IFG 02Bh
Port P2 direction P2DIR 02Ah
Port P2 output P2OUT 029h
Port P2 input P2IN 028h