Datasheet

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SLAS272F − JULY 2000 − REVISED JUNE 2004
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
comparator_A
The primary function of the comparator_A module is to support precision slope analog−to−digital conversions,
battery−voltage supervision, and monitoring of external analog signals.
ADC12 (Not implemented in the MSP430x14x1)
The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator and a 16 word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without
any CPU intervention.
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input Pin Number Device Input Signal Module Input Name Module Block Module Output Signal Output Pin Number
12 - P1.0 TACLK TACLK
ACLK ACLK
Timer
NA
SMCLK SMCLK
Timer NA
21 - P2.1 TAINCLK INCLK
13 - P1.1 TA0 CCI0A
13 - P1.1
22 - P2.2 TA0 CCI0B
CCR0
TA0
17 - P1.5
DV
SS
GND
CCR0 TA0
27 - P2.7
DV
CC
V
CC
14 - P1.2 TA1 CCI1A
14 - P1.2
CAOUT (internal) CCI1B
CCR1
TA1
18 - P1.6
DV
SS
GND
CCR1 TA1
23 - P2.3
DV
CC
V
CC
ADC12 (internal)
15 - P1.3 TA2 CCI2A
15 - P1.3
ACLK (internal) CCI2B
CCR2
TA2
19 - P1.7
DV
SS
GND
CCR2 TA2
24 - P2.4
DV
CC
V
CC
timer_B3 (MSP430x13x Only)
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.