Datasheet

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SLAS361D − JANUARY 2002 − REVISED AUGUST 2004
9
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interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh-0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
Power-up
External reset
Watchdog
Flash memory
WDTIFG (see Note1)
KEYV (see Note 1)
Reset 0FFFEh 15, highest
NMI
Oscillator fault
Flash memory access violation
NMIIFG (see Notes 1 and 4)
OFIFG (see Notes 1 and 4)
ACCVIFG (see Notes 1 and 4)
(Non)-maskable
(Non)-maskable
(Non)-maskable
0FFFCh 14
0FFFAh 13
0FFF8h 12
0FFF6h 11
Watchdog timer WDTIFG Maskable 0FFF4h 10
Timer_A3 TACCR0 CCIFG (see Note 2) Maskable 0FFF2h 9
Timer_A3
TACCR1 and TACCR2
CCIFGs, TAIFG
(see Notes 1 and 2)
Maskable 0FFF0h 8
USART0 receive (see Note 5) URXIFG0 Maskable 0FFEEh 7
USART0 transmit (see Note 5) UTXIFG0 Maskable 0FFECh 6
ADC10 ADC10IFG Maskable 0FFEAh 5
0FFE8h 4
I/O Port P2
(eight flags − see Note 3)
P2IFG.0 to P2IFG.7
(see Notes 1 and 2)
Maskable 0FFE6h 3
I/O Port P1
(eight flags)
P1IFG.0 to P1IFG.7
(see Notes 1 and 2)
Maskable 0FFE4h 2
0FFE2h 1
0FFE0h 0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module
3. There are eight Port P2 interrupt flags, but only six Port P2 I/O pins (P2.0−5) are implemented on the ’11x2 and ’12x2 devices.
4. (Non)-maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot.
5. USART0 is implemented in MSP430x12x2 devices only.