Datasheet

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SLAS361D − JANUARY 2002 − REVISED AUGUST 2004
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
10-bit ADC, timing parameters
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
For specified performance of
ADC10SR = 0 0.450 6.3
f
ADC10CLK
For specified performance of
ADC10 linearity parameters
ADC10SR = 1 0.450 1.5
MHz
f
ADC10OSC
ADC10DIV=0,
f
ADC10CLK
=f
ADC10OSC
V
CC
=
2.2 V/ 3V
3.7 6.3 MHz
t Conversion time
Internal oscillator,
f
ADC10OSC
= 3.7 MHz to
6.3 MHz
V
CC
=
2.2 V/ 3 V
2.06 3.51 µs
t
CONVERT
Conversion time
External f
ADC10CLK
from ACLK, MCLK or SMCLK:
ADC10SSEL ≠ 0
13×ADC10DIV×
1/f
ADC10CLK
µs
t
ADC10ON
‡
Turn on settling time of
the ADC
(see Note 1) 100 ns
R
S
= 400 Ω, R
I
= 2000 Ω,
V
CC
= 3 V 1400
t
Sample
‡
Sampling time
R
S
= 400
Ω
, R
I
= 2000
Ω
,
C
I
= 20 pF (see Note 2)
V
CC
= 2.2 V 1400
ns
†
Not production tested, limits characterized
‡
Not production tested, limits verified by design
NOTES: 1. The condition is that the error in a conversion started after t
ADC10ON
is less than ±0.5 LSB. The reference and input signal are already
settled.
2. Approximately eight Tau (τ) are needed to get an error of less than ±0.5 LSB.
t
Sample
= ln(2
n+1
) x (R
S
+ R
I
) x C
I
+ 800 ns. (ADC10SR = 0, n = ADC resolution = 10, R
S
= external source resistance)
t
Sample
= ln(2
n+1
) x (R
S
+ R
I
) x C
I
+ 2.5 µs. (ADC10SR = 1, n = ADC resolution = 10, R
S
= external source resistance)
10-bit ADC, linearity parameters
PARAMETER TEST CONDITIONS V
CC
MIN NOM MAX UNIT
1.4 V ≤ (V
eREF+
− V
REF−
/V
eREF−
) min ≤ 1.6 V ±1
E
I
Integral linearity error
1.6 V < (V
eREF+
− V
REF−
/V
eREF−
) min ≤ [V
CC
]
2.2 V/3 V
±1
LSB
E
D
Differential linearity
error
(V
eREF+
− V
REF−
/V
eREF−
)
min
≤ (V
eREF+
− V
REF−
/V
eREF−
) 2.2 V/3 V ±1 LSB
E
O
Offset error
(V
eREF+
− V
REF−
/V
eREF−
)
min
≤ (V
eREF+
− V
REF−
/V
eREF−
),
Internal impedance of source R
S
< 100 Ω,
2.2 V/3 V ±2 ±4 LSB
E
G
Gain error
(V
eREF+
− V
REF−
/V
eREF−
)
min
≤ (V
eREF+
− V
REF−
/V
eREF−
), 2.2 V/3 V ±1.1 ±2 LSB
E
T
Total unadjusted
error
(V
eREF+
− V
REF−
/V
eREF−
)
min
≤ (V
eREF+
− V
REF−
/V
eREF−
), 2.2 V/3 V ±2 ±5 LSB