Datasheet

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  
SLAS361D − JANUARY 2002 − REVISED AUGUST 2004
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Port P2, P2.3 to P2.4, input/output with Schmitt-trigger (continued)
PnSel.x PnDIR.x
DIRECTION
CONTROL
FROM MODULE
PnOUT.x MODULE X OUT PnIN.x MODULE X IN PnIE.x PnIFG.x PnIES.x
P2Sel.3 P2DIR.3 P2DIR.3 P2OUT.3 Out1 signal
†
P2IN.3 CCI1B
†
P2IE.3 P2IFG.3 P1IES.3
P2Sel.4 P2DIR.4 P2DIR.4 P2OUT.4 Out2 signal
†
P2IN.4 Unused P2IE.4 P2IFG.4 P1IES.4
†
Timer_A
input/output schematic (continued)
Port P2, P2.5, input/output with Schmitt-trigger and R
OSC
function for the Basic Clock Module
EN
D
P2.5/R
OSC
0
1
0
1
Interrupt
Edge
Select
EN
Set
Q
P2IE.5
P2IFG.5
P2IRQ.5
Interrupt
Flag
P2IES.5
P2SEL.5
Module X IN
P2IN.5
P2OUT.5
Module X OUT
Direction Control
From Module
P2DIR.5
P2SEL.5
Pad Logic
NOTE: DCOR: Control bit from Basic Clock Module: if it is set P2.5 is disconnected from P2.5 pad.
Bus Keeper
0
1
0
1
V
CC
Internal to
Basic Clock
Module
DCOR
DC
Generator
0: Input
1: Output
PnSel.x PnDIR.x
DIRECTION
CONTROL
FROM MODULE
PnOUT.x MODULE X OUT PnIN.x MODULE X IN PnIE.x PnIFG.x PnIES.x
P2Sel.5 P2DIR.5 P2DIR.5 P2OUT.5 V
SS
P2IN.5 unused P2IE.5 P2IFG.5 P2IES.5