Datasheet

 
  
SLAS361D − JANUARY 2002 − REVISED AUGUST 2004
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input Pin Number
Output Pin Number
DW and PW RHB
Device Input Module Module Module Output
DW and PW RHB
’11x2
20-Pin
’12x2
28-Pin
’11x2/12x2
32-Pin
Device Input
Signal
Module
Input Name
Module
Block
Module Output
Signal
’11x2
20-Pin
’12x2
28-Pin
’11x2/12x2
32-Pin
13 - P1.0 21 - P1.0 21 - P1.0 TACLK TACLK
ACLK ACLK
SMCLK SMCLK
Timer NA
9 - P2.1 9 - P2.1 7 - P2.1 INCLK INCLK
14 - P1.1 22 - P1.1 22 - P1.1 TA0 CCI0A
14 - P1.1 22 - P1.1 22 - P1.1
10 - P2.2 10 - P2.2 8 - P2.2 TA0 CCI0B
18 - P1.5 26 - P1.5 26 - P1.5
DV
SS
GND
CCR0 TA0
10 - P2.2 10 - P2.2 8 - P2.2
DV
CC
V
CC
ADC10 Internal
15 - P1.2 23 - P1.2 23 - P1.2 TA1 CCI1A
15 - P1.2 23 - P1.2 23 - P1.2
11 - P2.3 19 - P2.3 18 - P2.3 TA1 CCI1B
19 - P1.6 27 - P1.6 27 - P1.6
DV
SS
GND
CCR1 TA1
11 - P2.3 19 - P2.3 18 - P2.3
DV
CC
V
CC
ADC10 Internal
16 - P1.3 24 - P1.3 24 - P1.3 TA2 CCI2A
16 - P1.3 24 - P1.3 24 - P1.3
ACLK (internal) CCI2B
20 - P1.7 28 - P1.7 28 - P1.7
DV
SS
GND
CCR2 TA2
12 - P2.4 20 - P2.4 19 - P2.4
DV
CC
V
CC
ADC10 Internal