Datasheet

MSP430BT5190
www.ti.com SLAS703A –APRIL 2010–REVISED AUGUST 2013
Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
Internal: SMCLK, ACLK
f
TA
Timer_A input clock frequency External: TACLK 1.8 V, 3 V 25 MHz
Duty cycle = 50% ± 10%
All capture inputs, Minimum pulse
t
TA,cap
Timer_A capture timing 1.8 V, 3 V 20 ns
duration required for capture
Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
Internal: SMCLK, ACLK
f
TB
Timer_B input clock frequency External: TBCLK 1.8 V, 3 V 25 MHz
Duty cycle = 50% ± 10%
All capture inputs, Minimum pulse
t
TB,cap
Timer_B capture timing 1.8 V, 3 V 20 ns
duration required for capture
USCI (UART Mode), Recommended Operating Conditions
PARAMETER CONDITIONS V
CC
MIN TYP MAX UNIT
Internal: SMCLK, ACLK
f
USCI
USCI input clock frequency External: UCLK f
SYSTEM
MHz
Duty cycle = 50% ± 10%
BITCLK clock frequency
f
BITCLK
1 MHz
(equals baud rate in MBaud)
USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
2.2 V 50 600
t
τ
UART receive deglitch time
(1)
ns
3 V 50 600
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
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