Datasheet

Basic
Clock
System+
16KB
8KB
4KB
Flash
MCLK
ACLK
SMCLK
12MHz
CPU
incl. 16
Registers
Emulation
2BP
XT2IN
XT2OUT
JTAG
Interface
Watchdog
WDT+
15/16-bit
SD24_A
(w/o BUF)
3 Converter
2 Converter
1 Converter
Timer_A3
3 CC
Registers
USART0
UART
or SPI
Function
DVCC
DVSS
AVCC
AVSS
512B
512B
256B
RAM
BOR
SVS/SVM
Spy-Bi
Wire
Hardware
Multiplier
(16x16)
MPY,
MPYS,
MAC,
MACS
Port P1
8 I/O
Interrupt
capability
Pull-up/
down
resistors
Port P2
3 I/O
Interrupt
capability
Pull-up/
down
resistors
RST/NMI
P1.x
8
P2.x
3
MAB
MDB
MSP430AFE2x3
1A0.0+
2A0.0-
3A1.0+
4A1.0-
5AVCC
6AVSS
7VREF
8A2.0+
9A2.0-
10TEST/SBWTCK
11
RST/NMI/SBWTDIO
12P1.0/SVSIN/TACLK/SMCLK/TA2 13 DVSS
14 P2.6/XT2IN
15 P2.7/XT2OUT
16 DVCC
17 P1.1/TA1/SDCLK
18 P1.2/TA0/SD0DO
19 P1.3/UTXD0/SD1DO
20 P1.4/URXD0/SD2DO
21 P1.5/SIMO0/SVSOUT/TMS
22 P1.6/SOMI0/TA2/TCK
23 P1.7/UCLK0/TA1/TDO/TDI
24 P2.0/STE0/TA0/TDI/TCLK
MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
www.ti.com SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
Functional Block Diagram
Pin Designation, MSP430AFE2x3IPW
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