Datasheet

BSLEN
RST/NMI
(DVIO domain)
t
V
IT-
V
IT+
V
IT+
t
SU,BSLEN
V
IT-
t
HO,BSLEN
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
www.ti.com SLAS718D –NOVEMBER 2012–REVISED OCTOBER 2013
DVIO BSL Entry
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER V
CC
V
IO
MIN TYP MAX UNIT
1.62 V to
t
SU, BSLEN
Setup time BSLEN to RST/NMI
(1)
2.2 V, 3 V 100 ns
1.98 V
1.62 V to
t
HO, BSLEN
Hold time BSLEN to RST/NMI
(2)
2.2 V, 3 V 350 µs
1.98 V
(1) AVCC, DVCC, DVIO stable and within specification.
(2) BSLEN must remain logically high long enough for the boot code to detect its level and enter the BSL sequence. After the minimum hold
time is achieved, BSLEN is a don't care.
Figure 19. DVIO BSL Entry Timing
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