Datasheet
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
SLAS718D –NOVEMBER 2012–REVISED OCTOBER 2013
www.ti.com
Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS
DV
CC(PGM/ERASE)
Program and erase supply voltage 1.8 3.6 V
I
PGM
Average supply current from DVCC during program 3 5 mA
I
ERASE
Average supply current from DVCC during erase 6 11 mA
Average supply current from DVCC during mass erase or bank
I
MERASE
, I
BANK
6 11 mA
erase
t
CPT
Cumulative program time See
(1)
16 ms
Program and erase endurance 10
4
10
5
cycles
t
Retention
Data retention duration T
J
= 25°C 100 years
t
Word
Word or byte program time See
(2)
64 85 µs
t
Block, 0
Block program time for first byte or word See
(2)
49 65 µs
Block program time for each additional byte or word, except for last
t
Block, 1–(N–1)
See
(2)
37 49 µs
byte or word
t
Block, N
Block program time for last byte or word See
(2)
55 73 µs
Erase time for segment, mass erase, and bank erase when
t
Erase
See
(2)
23 32 ms
available
MCLK frequency in marginal read mode
f
MCLK,MGR
0 1 MHz
(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1)
(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word or byte write mode and block write mode.
(2) These values are hardwired into the flash controller's state machine.
JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER V
CC
V
IO
MIN TYP MAX UNIT
1.62 V to
f
SBW
Spy-Bi-Wire input frequency 2.2 V, 3 V 0 20 MHz
1.98 V
1.62 V to
t
SBW,Low
Spy-Bi-Wire low clock pulse length 2.2 V, 3 V 0.025 15 µs
1.98 V
Spy-Bi-Wire enable time (TEST high to acceptance of first 1.62 V to
t
SBW, En
2.2 V, 3 V 1 µs
clock edge)
(1)
1.98 V
1.62 V to
t
SBW,Rst
Spy-Bi-Wire return to normal operation time 2.2 V, 3 V 15 100 µs
1.98 V
1.62 V to
2.2 V 0 5 MHz
1.98 V
f
TCK
TCK input frequency for 4-wire JTAG
(2)
1.62 V to
3 V 0 10 MHz
1.98 V
1.62 V to
R
internal
Internal pulldown resistance on TEST 2.2 V, 3 V 45 60 80 kΩ
1.98 V
(1) Tools accessing the Spy-Bi-Wire interface need to wait for the t
SBW,En
time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
(2) f
TCK
may be restricted to meet the timing requirements of the module selected.
78 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217
MSP430F5214 MSP430F5212