Datasheet

SDA
SCL
t
HD,DAT
t
SU,DAT
t
HD,STA
t
HIGH
t
LOW
t
BUF
t
HD,STA
t
SU,STA
t
SP
t
SU,STO
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
www.ti.com SLAS718D –NOVEMBER 2012–REVISED OCTOBER 2013
USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 18)
PARAMETER TEST CONDITIONS V
CC
V
IO
(1)
MIN TYP MAX UNIT
Internal: SMCLK or ACLK,
f
USCI
USCI input clock frequency External: UCLK f
SYSTEM
MHz
Duty cycle = 50% ± 10%
f
SCL
SCL clock frequency 2.2 V, 3 V 1.62 V to 1.98 V 0 400 kHz
f
SCL
≤ 100 kHz 4.0
t
HD,STA
Hold time (repeated) START 2.2 V, 3 V 1.62 V to 1.98 V µs
f
SCL
> 100 kHz 0.6
f
SCL
≤ 100 kHz 4.7
Setup time for a repeated
t
SU,STA
2.2 V, 3 V 1.62 V to 1.98 V µs
START
f
SCL
> 100 kHz 0.6
t
HD,DAT
Data hold time 2.2 V, 3 V 1.62 V to 1.98 V 0 ns
t
SU,DAT
Data setup time 2.2 V, 3 V 1.62 V to 1.98 V 250 ns
f
SCL
≤ 100 kHz 4.0
t
SU,STO
Setup time for STOP 2.2 V, 3 V 1.62 V to 1.98 V µs
f
SCL
> 100 kHz 0.6
Pulse duration of spikes
t
SP
2.2 V, 3 V 1.62 V to 1.98 V 50 600 ns
suppressed by input filter
(1) In all test conditions, V
IO
≤ V
CC
Figure 18. I2C Mode Timing
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