Datasheet
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
www.ti.com
SLAS718D –NOVEMBER 2012–REVISED OCTOBER 2013
USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Note
(1)
, Figure 16 and Figure 17)
PARAMETER TEST CONDITIONS V
CC
V
IO
MIN TYP MAX UNIT
1.8 V 1.62 V to 1.80 V 12
PMMCOREV = 0 ns
3.0 V 1.62 V to 1.98 V 12
t
STE,LEAD
STE lead time, STE low to clock
2.4 V 1.62 V to 1.98 V 10
PMMCOREV = 3 ns
3.0 V 1.62 V to 1.98 V 10
1.8 V 1.62 V to 1.80 V 6
PMMCOREV = 0 ns
3.0 V 1.62 V to 1.98 V 6
STE lag time, Last clock to STE
t
STE,LAG
high
2.4 V 1.62 V to 1.98 V 6
PMMCOREV = 3 ns
3.0 V 1.62 V to 1.98 V 6
1.8 V 1.62 V to 1.80 V 65
PMMCOREV = 0 ns
3.0 V 1.62 V to 1.98 V 65
STE access time, STE low to
t
STE,ACC
SOMI data out
2.4 V 1.62 V to 1.98 V 45
PMMCOREV = 3 ns
3.0 V 1.62 V to 1.98 V 45
1.8 V 1.62 V to 1.80 V 35
PMMCOREV = 0 ns
3.0 V 1.62 V to 1.98 V 35
STE disable time, STE high to
t
STE,DIS
SOMI high impedance
2.4 V 1.62 V to 1.98 V 25
PMMCOREV = 3 ns
3.0 V 1.62 V to 1.98 V 25
1.8 V 1.62 V to 1.80 V 5
PMMCOREV = 0 ns
3.0 V 1.62 V to 1.98 V 5
t
SU,SI
SIMO input data setup time
2.4 V 1.62 V to 1.98 V 5
PMMCOREV = 3 ns
3.0 V 1.62 V to 1.98 V 5
1.8 V 1.62 V to 1.80 V 5
PMMCOREV = 0 ns
3.0 V 1.62 V to 1.98 V 5
t
HD,SI
SIMO input data hold time
2.4 V 1.62 V to 1.98 V 5
PMMCOREV = 3 ns
3.0 V 1.62 V to 1.98 V 5
UCLK edge to SOMI valid, 1.8 V 1.62 V to 1.80 V 75
C
L
= 20 pF, ns
3.0 V 1.62 V to 1.98 V 75
PMMCOREV = 0
t
VALID,SO
SOMI output data valid time
(2)
UCLK edge to SOMI valid, 2.4 V 1.62 V to 1.98 V 50
C
L
= 20 pF, ns
3.0 V 1.62 V to 1.98 V 50
PMMCOREV = 3
1.8 V 1.62 V to 1.80 V 18
C
L
= 20 pF,
ns
PMMCOREV = 0
3.0 V 1.62 V to 1.98 V 18
t
HD,SO
SOMI output data hold time
(3)
2.4 V 1.62 V to 1.98 V 10
C
L
= 20 pF,
ns
PMMCOREV = 3
3.0 V 1.62 V to 1.98 V 10
(1) f
UCxCLK
= 1/2t
LO/HI
with t
LO/HI
≥ max(t
VALID,MO(Master)
+ t
SU,SI(USCI)
, t
SU,MI(Master)
+ t
VALID,SO(USCI)
).
For the master's parameters t
SU,MI(Master)
and t
VALID,MO(Master)
see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 14 and Figure 15.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 14
and Figure 15.
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