Datasheet
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
www.ti.com
SLAS718D –NOVEMBER 2012–REVISED OCTOBER 2013
Output Frequency – General-Purpose I/O DVCC Domain
(P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
V
CC
= 1.8 V,
16
PMMCOREVx = 0
Port output frequency
f
Px.y
(1)(2)
MHz
(with load)
V
CC
= 3 V,
25
PMMCOREVx = 3
V
CC
= 1.8 V,
16
PMMCOREVx = 0
ACLK, SMCLK, or MCLK,
f
Port_CLK
Clock output frequency MHz
C
L
= 20 pF
(2)
V
CC
= 3 V,
25
PMMCOREVx = 3
(1) A resistive divider with 2 × R1 between V
CC
and V
SS
is used as load. The output is connected to the center tap of the divider. For full
drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. C
L
= 20 pF is connected to the output to V
SS
.
(2) The output voltage reaches at least 10% and 90% V
CC
at the specified toggle frequency.
Output Frequency – General-Purpose I/O DVIO Domain
(P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
V
IO
= 1.62 V to 1.98 V
(3)
,
16
PMMCOREVx = 0
Port output frequency
f
Px.y
(1)(2)
MHz
(with load)
V
IO
= 1.62 V to 1.98 V
(3)
,
25
PMMCOREVx = 3
V
IO
= 1.62 V to 1.98 V
(3)
,
16
PMMCOREVx = 0
ACLK, SMCLK, or MCLK,
f
Port_CLK
Clock output frequency MHz
C
L
= 20 pF
(2)
V
IO
= 1.62 V to 1.98 V
(3)
,
25
PMMCOREVx = 3
(1) A resistive divider with 2 × R1 between V
IO
and V
SS
is used as load. The output is connected to the center tap of the divider. For full
drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. C
L
= 20 pF is connected to the output to V
SS
.
(2) The output voltage reaches at least 10% and 90% V
IO
at the specified toggle frequency.
(3) In all test conditions, V
IO
≤ V
CC
.
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