Datasheet

V
(SVSH_+), min
V
CC
V
CC
V
CC
RSTDVCC
V
IO
V
IO
V
CC
≥ V
RSTDVCC
DVCC
V = V
RSTDVCC CC
DVIO
RST
V
IO
≥ V
RST
V = V
RST IO
t
t
WAKE_UP_RESET
V
IT+
t
WAKE_UP_RESET
V
IT+
t
WAKE_UP_RESET
t
WAKE_UP_RESET
t
WAKE_UP_RESET
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
SLAS718D –NOVEMBER 2012–REVISED OCTOBER 2013 www.ti.com
NOTE: The device remains in reset based on the conditions of the RSTDVCC and RST pins and the voltage present on
DVCC voltage supply. If RSTDVCC or RST is held at a logic low or if DVCC is below the SVSH_+ minimum
threshold, the device remains in its reset condition; that is, these conditions form a logical OR with respect to device
reset.
Figure 3. Reset Timing
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Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217
MSP430F5214 MSP430F5212