Datasheet
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
SLAS718D –NOVEMBER 2012–REVISED OCTOBER 2013
www.ti.com
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
Voltage applied at V
CC
to V
SS
-0.3 V to 4.1 V
Voltage applied at V
IO
to V
SS
-0.3 V to 2.2 V
Voltage applied to any pin (excluding VCORE and V
IO
pins)
(2)
-0.3 V to (V
CC
+ 0.3 V)
Voltage applied to V
IO
pins -0.3 V to (V
IO
+ 0.2 V)
Diode current at any device pin ±2 mA
Storage temperature range, T
stg
(3)
-55°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings " may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to V
SS
. VCORE is for internal device use only. No external DC loading or voltage should be applied.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Recommended Operating Conditions
Typical values are specified at V
CC
= 3.3 V and T
A
= 25°C (unless otherwise noted)
MIN NOM MAX UNIT
PMMCOREVx = 0 1.8 3.6 V
PMMCOREVx = 0, 1 2.0 3.6 V
Supply voltage during program execution and flash
V
CC
programming(AVCC = DVCC)
(1)(2)(3)
PMMCOREVx = 0, 1, 2 2.2 3.6 V
PMMCOREVx = 0, 1, 2, 3 2.4 3.6 V
V
IO
Supply voltage applied to DVIO referenced to V
SS
(2)
1.62 1.98 V
V
SS
Supply voltage (AVSS = DVSS) 0 V
T
A
Operating free-air temperature I version -40 85 °C
T
J
Operating junction temperature I version -40 85 °C
C
VCORE
Recommended capacitor at VCORE
(4)
470 nF
C
DVCC
/
Capacitor ratio of DVCC to VCORE 10
C
VCORE
PMMCOREVx = 0 (default
condition), 0 8
1.8 V ≤ V
CC
≤ 3.6 V
PMMCOREVx = 1,
0 12
Processor frequency (maximum MCLK frequency)
(5)
2.0 V ≤ V
CC
≤ 3.6 V
f
SYSTEM
MHz
(see Figure 4)
PMMCOREVx = 2,
0 20
2.2 V ≤ V
CC
≤ 3.6 V
PMMCOREVx = 3,
0 25
2.4 V ≤ V
CC
≤ 3.6 V
(1) It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
(2) During V
CC
and V
IO
power up, it is required that V
IO
≥ V
CC
during the ramp up phase of V
IO
. During V
CC
and V
IO
power down, it is
required that V
IO
≥ V
CC
during the ramp down phase of V
IO
(see Figure 2).
(3) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the PMM, SVS High Side threshold
parameters for the exact values and further details.
(4) A capacitor tolerance of ±20% or better is required.
(5) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
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