Datasheet

MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
SLAS718D –NOVEMBER 2012–REVISED OCTOBER 2013 www.ti.com
TA0 (Link to user's guide)
TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. It can support multiple captures
or compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be
generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 14. TA0 Signal Connections
INPUT PIN NUMBER OUTPUT PIN NUMBER
DEVICE MODULE MODULE DEVICE
MODULE
INPUT INPUT OUTPUT OUTPUT
RGC, ZQE,
BLOCK
RGZ RGC, ZQE, YFF RGZ
SIGNAL SIGNAL SIGNAL SIGNAL
YFF
18, H2, G2-
13-P1.0 TA0CLK TACLK
P1.0
ACLK
ACLK
(internal)
Timer NA NA
SMCLK
SMCLK
(internal)
18, H2, G2-
13-P1.0 TA0CLK TACLK
P1.0
19, H3, G3-
14-P1.1 TA0.0 CCI0A 19, H3, G3-P1.1 14-P1.1
P1.1
DVSS CCI0B
CCR0 TA0 TA0.0
DVSS GND
DVCC V
CC
20, J3, H3-
15-P1.2 TA0.1 CCI1A 20, J3, H3-P1.2 15-P1.2
P1.2
ADC10 (internal) ADC10 (internal)
CBOUT
CCI1B ADC10SHSx = ADC10SHSx =
CCR1 TA1 TA0.1
(internal)
{1} {1}
DVSS GND
DVCC V
CC
21, G4, F3-
16-P1.3 TA0.2 CCI2A 21, G4, F3-P1.3 16-P1.3
P1.3
ACLK
CCI2B
CCR2 TA2 TA0.2
(internal)
DVSS GND
DVCC V
CC
22, H4, E3-
17-P1.4 TA0.3 CCI3A 22, H4, E3-P1.4 17-P1.4
P1.4
DVSS CCI3B
CCR3 TA3 TA0.3
DVSS GND
DVCC V
CC
23, J4, H4-
18-P1.5 TA0.4 CCI4A 23, J4, H4-P1.5 18-P1.5
P1.5
DVSS CCI4B
CCR4 TA4 TA0.4
DVSS GND
DVCC V
CC
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MSP430F5214 MSP430F5212