Datasheet

Unified
Clock
System
128KB
64KB
Flash
8KB
RAM
MCLK
ACLK
SMCLK
CPUXV2
and
Working
Registers
EEM
(S: 3+1)
XIN
XOUT
JTAG,
SBW
Interface
DMA
3 Channel
XT2IN
XT2OUT
Power
Management
LDO
SVM/SVS
Brownout
SYS
Watchdog
Port Map
Control
(P4)
MPY32
TA0
Timer_A
5 CC
Registers
TA1
Timer_A
3 CC
Registers
TB0
Timer_B
7 CC
Registers
RTC_A
CRC16
ADC10_A
200 KSPS
12 Channels
(10 ext,2 int)
10 Bit
DVCC
DVSS
RST/NMI
TA2
Timer_A
3 CC
Registers
REF
VCORE
MAB
MDB
COMP_B
8 Channels
DVIO
AVCC
AVSS
BSLEN
USCI0,1
USCI_Ax:
UART,
IrDA, SPI
USCI_Bx:
SPI, I2C
PA
PB PC
P1.x P2.x
P3.x
P4.x
P5.x P6.x
PD
P7.x
PJ
PJ.x
P4
1×8 I/Os
P5
1×6 I/Os
P6
1×8 I/Os
P7
1×6 I/Os
PJ
1×4 I/Os
P1
1×4 I/Os
P2
1×8 I/Os
P1
1×4 I/Os
I/O Ports
Interrupt and Wakeup
PA
1×16 I/Os
P3
1×5 I/Os
PB
1×13 I/Os
PC
1×14 I/Os
PD
1×6 I/Os
I/O Ports
I/O are supplied by DVIO
RSTDVCC
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
www.ti.com SLAS718D –NOVEMBER 2012–REVISED OCTOBER 2013
Functional Block Diagram – F5229, F5227 – RGC, ZQE, YFF Packages
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Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217
MSP430F5214 MSP430F5212