Datasheet
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
www.ti.com
SLAS718D –NOVEMBER 2012–REVISED OCTOBER 2013
Table 10. Port Mapping Mnemonics and Functions (continued)
VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
PM_UCA0TXD USCI_A0 UART TXD (direction controlled by USCI - output)
21
PM_UCA0SIMO USCI_A0 SPI slave in master out (direction controlled by USCI)
PM_UCA0CLK USCI_A0 clock input/output (direction controlled by USCI)
22
PM_UCB0STE USCI_B0 SPI slave transmit enable (direction controlled by USCI)
PM_UCB0SOMI USCI_B0 SPI slave out master in (direction controlled by USCI)
23
PM_UCB0SCL USCI_B0 I2C clock (open drain and direction controlled by USCI)
PM_UCB0SIMO USCI_B0 SPI slave in master out (direction controlled by USCI)
24
PM_UCB0SDA USCI_B0 I2C data (open drain and direction controlled by USCI)
PM_UCB0CLK USCI_B0 clock input/output (direction controlled by USCI)
25
PM_UCA0STE USCI_A0 SPI slave transmit enable (direction controlled by USCI)
26 - 30 Reserved None DVSS
Disables the output driver and the input Schmitt trigger to prevent parasitic
31 (0FFh)
(1)
PM_ANALOG
cross currents when applying analog signals
(1) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored
resulting in a read out value of 31.
Table 11. Default Mapping
PIN PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
USCI_B1 SPI slave transmit enable (direction controlled by USCI)
P4.0/P4MAP0 PM_UCB1STE/PM_UCA1CLK
USCI_A1 clock input/output (direction controlled by USCI)
USCI_B1 SPI slave in master out (direction controlled by USCI)
P4.1/P4MAP1 PM_UCB1SIMO/PM_UCB1SDA
USCI_B1 I2C data (open drain and direction controlled by USCI)
USCI_B1 SPI slave out master in (direction controlled by USCI)
P4.2/P4MAP2 PM_UCB1SOMI/PM_UCB1SCL
USCI_B1 I2C clock (open drain and direction controlled by USCI)
USCI_A1 SPI slave transmit enable (direction controlled by USCI)
P4.3/P4MAP3 PM_UCB1CLK/PM_UCA1STE
USCI_B1 clock input/output (direction controlled by USCI)
USCI_A1 UART TXD (Direction controlled by USCI - output)
P4.4/P4MAP4 PM_UCA1TXD/PM_UCA1SIMO
USCI_A1 SPI slave in master out (direction controlled by USCI)
USCI_A1 UART RXD (Direction controlled by USCI - input)
P4.5/P4MAP5 PM_UCA1RXD/PM_UCA1SOMI
USCI_A1 SPI slave out master in (direction controlled by USCI)
P4.6/P4MAP6 PM_NONE None DVSS
P4.7/P4MAP7
(1)
PM_NONE None DVSS
(1) Not available on all devices
Oscillator and System Clock (Link to user's guide)
The clock system in the MSP430F522x and MSP430F521x family of devices is supported by the Unified Clock
System (UCS) module, which includes support for a 32-kHz watch crystal oscillator (XT1 LF mode) (XT1 HF
mode is not supported), an internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-
frequency oscillator (REFO), an integrated internal digitally controlled oscillator (DCO), and a high-frequency
crystal oscillator (XT2). The UCS module is designed to meet the requirements of both low system cost and low
power consumption. The UCS module features digital frequency locked loop (FLL) hardware that, in conjunction
with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the selected FLL reference
frequency. The internal DCO provides a fast turn-on clock source and stabilizes in 3.5 µs (typical). The UCS
module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (XT1), a high-frequency crystal (XT2), the
internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitally
controlled oscillator DCO.
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made
available to ACLK.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by
same sources made available to ACLK.
• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
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MSP430F5214 MSP430F5212