Datasheet
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
SLAS718D –NOVEMBER 2012–REVISED OCTOBER 2013
www.ti.com
• Three Channel Internal DMA • For Design Guidelines, See Designing With
MSP430F522x Devices (SLAA558)
• Basic Timer With Real-Time Clock (RTC)
Feature
APPLICATIONS
• Table 1 Summarizes Available Family
• Analog and Digital Sensor Systems
Members
• Data Loggers
• For Complete Module Descriptions, See the
MSP430x5xx and MSP430x6xx Family User's
• General-Purpose Applications
Guide (SLAU208)
DESCRIPTION
The Texas Instruments MSP430™ family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with extensive low-
power modes, is optimized to achieve extended battery life in portable measurement applications. The device
features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from low-power modes to active
mode in 3.5 µs (typical).
The MSP430F522x series are microcontroller configurations with four 16-bit timers, a high-performance 10-bit
analog-to-digital converter (ADC), two universal serial communication interfaces (USCIs), a hardware multiplier,
DMA, a comparator, and a real-time clock (RTC) module with alarm capabilities. The MSP430F521x series
include all of the peripherals of the MSP430F522x series with the exception of the ADC. All devices have a split
I/O supply system that allows for a seamless interface to other devices that have a nominal 1.8-V I/O interface
without the need for external level translation.
Typical applications include analog and digital sensor systems, data loggers, and various general-purpose
applications.
Table 1 summarizes the available family members.
Table 1. Family Members
(1)(2)
USCI
Flash SRAM ADC10_A Comp_B I/O I/O Package
Channel A: Channel B:
Device Timer_A
(3)
Timer_B
(4)
(KB) (KB) (Ch) (Ch) DVCC
(5)
DVIO
(6)
Type
UART, IrDA,
SPI, I
2
C
SPI
64 RGC
10 ext,
MSP430F5229 128 8 5, 3, 3 7 2 2 8 22 31 64 YFF
2 int
80 ZQE
64 RGC
10 ext,
MSP430F5227 64 8 5, 3, 3 7 2 2 8 22 31 64 YFF
2 int
80 ZQE
MSP430F5224 128 8 5, 3, 3 7 2 2 8 ext, 2 int 6 20 17 48 RGZ
MSP430F5222 64 8 5, 3, 3 7 2 2 8 ext, 2 int 6 20 17 48 RGZ
64 RGC
MSP430F5219 128 8 5, 3, 3 7 2 2 - 8 22 31 64 YFF
80 ZQE
64 RGC
MSP430F5217 64 8 5, 3, 3 7 2 2 - 8 22 31 64 YFF
80 ZQE
MSP430F5214 128 8 5, 3, 3 7 2 2 - 6 20 17 48 RGZ
MSP430F5212 64 8 5, 3, 3 7 2 2 - 6 20 17 48 RGZ
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/packaging.
(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(5) All of these I/O reside on a single voltage rail supplied by DVCC.
(6) All of these I/O reside on a single voltage rail supplied by DVIO.
2 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217
MSP430F5214 MSP430F5212