Datasheet
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
SLAS718D –NOVEMBER 2012–REVISED OCTOBER 2013
www.ti.com
Table 3. Terminal Functions (continued)
TERMINAL
NO. I/O
(1)
DESCRIPTION
NAME
RGC ZQE YFF RGZ
General-purpose digital I/O (not available on all device types)
B8,
P7.0/TB0.0
(7)
49 H1 N/A I/O
TB0 CCR0 capture: CCI0A input, compare: Out0 output (not available on
B9
all device types)
General-purpose digital I/O (not available on all device types)
P7.1/TB0.1
(7)
50 A9 G2 N/A I/O
TB0 CCR1 capture: CCI1A input, compare: Out1 output (not available on
all device types)
General-purpose digital I/O (not available on all device types)
P7.2/TB0.2
(7)
51 B7 F3 N/A I/O
TB0 CCR2 capture: CCI2A input, compare: Out2 output (not available on
all device types)
General-purpose digital I/O (not available on all device types)
P7.3/TB0.3
(7)
52 A8 G1 N/A I/O
TB0 CCR3 capture: CCI3A input, compare: Out3 output (not available on
all device types)
General-purpose digital I/O (not available on all device types)
P7.4/TB0.4
(7)
53 A7 F2 N/A I/O
TB0 CCR4 capture: CCI4A input, compare: Out4 output (not available on
all device types)
General-purpose digital I/O (not available on all device types)
P7.5/TB0.5
(7)
54 A6 F1 N/A I/O
TB0 CCR5 capture: CCI5A input, compare: Out5 output (not available on
all device types)
BSLEN
(8)
55 B6 E2 36 I BSL enable with internal pulldown
Reset input active low
(9)(10)
RST/NMI
(8)
56 A5 E3 37 I
Non-maskable interrupt input
(9)
General-purpose digital I/O
P5.2/XT2IN 57 B5 E1 38 I/O
Input terminal for crystal oscillator XT2
(11)
General-purpose digital I/O
P5.3/XT2OUT 58 B4 D1 39 I/O
Output terminal of crystal oscillator XT2
Test mode pin – Selects four wire JTAG operation
TEST/SBWTCK
(12)
59 A4 E4 40 I
Spy-Bi-Wire input clock when Spy-Bi-Wire operation activated
General-purpose digital I/O
PJ.0/TDO
(13)
60 C5 D2 41 I/O
JTAG test data output port
General-purpose digital I/O
PJ.1/TDI/TCLK
(13)
61 C4 C1 42 I/O
JTAG test data input or test clock input
General-purpose digital I/O
PJ.2/TMS
(13)
62 A3 D3 43 I/O
JTAG test mode select
General-purpose digital I/O
PJ.3/TCK
(13)
63 B3 B1 44 I/O
JTAG test clock
Reset input active low
(14)
RSTDVCC/SBWTDIO
(13)
64 A2 D4 45 I/O
Spy-Bi-Wire data input/output when Spy-Bi-Wire operation activated
(8) This pin function is supplied by DVIO. See Electrical Characteristics for input and output requirements.
(9) This pin is configurable as reset or NMI and resides on the DVIO supply domain. When driven from external, the input swing levels from
DVSS to DVIO are required.
(10) When this pin is configured as reset, the internal pullup resistor is enabled by default.
(11) When in crystal bypass mode, XT2IN can be configured so that it can support an input digital waveform with swing levels from DVSS to
DVCC or DVSS to DVIO. In this case, it is required that the pin be configured properly for the intended input swing.
(12) See Bootstrap Loader (BSL) and JTAG Operation for use with BSL and JTAG functions.
(13) See JTAG Operation for use with JTAG function.
(14) This non-configurable reset resides on the DVCC supply domain and has an internal pullup to DVCC. When driven from external, input
swing levels from DVSS to DVCC are required. This reset must be used for Spy-Bi-Wire communication and is not the same RST/NMI
reset as found on other devices in the MSP430 family. See Bootstrap Loader (BSL) and JTAG Operation for details regarding the use of
this pin.
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Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217
MSP430F5214 MSP430F5212