Datasheet

MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
www.ti.com SLAS718D –NOVEMBER 2012–REVISED OCTOBER 2013
Table 3. Terminal Functions
TERMINAL
NO. I/O
(1)
DESCRIPTION
NAME
RGC ZQE YFF RGZ
General-purpose digital I/O
P6.4/CB4/A4 5 C1 A2 2 I/O
Comparator_B input CB4
Analog input A4 – ADC (not available on all device types)
General-purpose digital I/O
P6.5/CB5/A5 6 D2 B3 3 I/O
Comparator_B input CB5
Analog input A5 – ADC (not available on all device types)
General-purpose digital I/O (not available on all device types)
P6.6/CB6/A6 7 D1 C4 N/A I/O
Comparator_B input CB6 (not available on all device types)
Analog input A6 – ADC (not available on all device types)
General-purpose digital I/O (not available on all device types)
P6.7/CB7/A7 8 D3 A3 N/A I/O
Comparator_B input CB7 (not available on all device types)
Analog input A7 – ADC (not available on all device types)
General-purpose digital I/O
Analog input A8 – ADC (not available on all device types)
P5.0/A8/VeREF+ 9 E1 B4 4 I/O
Input for an external reference voltage to the ADC (not available on all
device types)
General-purpose digital I/O
Analog input A9 – ADC (not available on all device types)
P5.1/A9/VeREF- 10 E2 A4 5 I/O
Negative terminal for the ADC's reference voltage for an external applied
reference voltage (not available on all device types)
AVCC 11 F2 B5 6 Analog power supply
General-purpose digital I/O
P5.4/XIN 12 F1 A5 7 I/O
Input terminal for crystal oscillator XT1
(2)
General-purpose digital I/O
P5.5/XOUT 13 G1 A6 8 I/O
Output terminal of crystal oscillator XT1
AVSS 14 G2 B6 9
Analog ground supply
DVCC 15 H1 A7 10
Digital power supply
DVSS 16 J1 A8 11
Digital ground supply
Regulated core power supply output (internal use only, no external
VCORE
(3)
17 J2 B8 12
current loading)
General-purpose digital I/O with port interrupt
P1.0/TA0CLK/ACLK 18 H2 B7 13 I/O
TA0 clock signal TA0CLK input
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
General-purpose digital I/O with port interrupt
P1.1/TA0.0 19 H3 C7 14 I/O
TA0 CCR0 capture: CCI0A input, compare: Out0 output
BSL transmit output
General-purpose digital I/O with port interrupt
P1.2/TA0.1 20 J3 C8 15 I/O
TA0 CCR1 capture: CCI1A input, compare: Out1 output
BSL receive input
General-purpose digital I/O with port interrupt
P1.3/TA0.2 21 G4 C6 16 I/O
TA0 CCR2 capture: CCI2A input, compare: Out2 output
(1) I = input, O = output, N/A = not available
(2) When in crystal bypass mode, XIN can be configured so that it can support an input digital waveform with swing levels from DVSS to
DVCC or DVSS to DVIO. In this case, it is required that the pin be configured properly for the intended input swing.
(3) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, C
VCORE
.
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