MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 MSP430F522x, MSP430F521x Mixed Signal Microcontroller Check for Samples: MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222, MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 FEATURES 1 • 2 • • • Dual-Supply Voltage Device – Primary Supply (AVCC, DVCC): – Powered From External Supply: 3.6 V Down to 1.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 • • www.ti.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Functional Block Diagram – F5229, F5227 – RGC, ZQE, YFF Packages XIN XOUT XT2IN XT2OUT Unified Clock System RSTDVCC RST/NMI BSLEN ACLK 8KB Power Management Flash RAM LDO SVM/SVS Brownout PA DVIO VCORE P1.x P2.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com P7.0/TB0.0 P7.1/TB0.1 P7.2/TB0.2 P7.3/TB0.3 P7.4/TB0.4 P7.5/TB0.5 BSLEN RST/NMI P5.2/XT2IN P5.3/XT2OUT TEST/SBWTCK PJ.0/TDO PJ.1/TDI/TCLK PJ.2/TMS PJ.3/TCK RSTDVCC/SBWTDIO Pin Designation – F5229, F5227 – RGC Package 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P6.0/A0/CB0 1 48 P4.7/PM_NONE P6.1/A1/CB1 2 47 P4.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Functional Block Diagram – F5224, F5222 – RGZ Package XIN XOUT RSTDVCC RST/NMI BSLEN DVCC AVCC DVSS AVSS PA DVIO VCORE P1.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com RST/NMI P5.2/XT2IN P5.3/XT2OUT TEST/SBWTCK PJ.0/TDO PJ.1/TDI/TCLK PJ.2/TMS PJ.3/TCK RSTDVCC/SBWTDIO P6.0/A0/CB0 P6.1/A1/CB1 P6.2/A2/CB2 Pin Designation – F5224, F5222 – RGZ Package 48 47 46 45 44 43 42 41 40 39 38 37 P6.3/A3/CB3 1 36 BSLEN P6.4/A4/CB4 2 35 P4.6/PM_NONE P6.5/A5/CB5 3 34 P4.5/PM_UCA1RXD/PM_UCA1SOMI P5.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Functional Block Diagram – F5219, F5217 – RGC, ZQE, YFF Packages XIN XOUT XT2IN XT2OUT Unified Clock System RSTDVCC RST/NMI BSLEN ACLK 8KB Power Management Flash RAM LDO SVM/SVS Brownout PA DVIO VCORE P1.x P2.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com P7.0/TB0.0 P7.1/TB0.1 P7.2/TB0.2 P7.3/TB0.3 P7.4/TB0.4 P7.5/TB0.5 BSLEN RST/NMI P5.2/XT2IN P5.3/XT2OUT TEST/SBWTCK PJ.0/TDO PJ.1/TDI/TCLK PJ.2/TMS PJ.3/TCK RSTDVCC/SBWTDIO Pin Designation – F5219, F5217 – RGC Package 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P6.0/CB0 1 48 P4.7/PM_NONE P6.1/CB1 2 47 P4.6/PM_NONE P6.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Functional Block Diagram – F5214, F5212 – RGZ Package XIN XOUT XT2IN XT2OUT Unified Clock System RSTDVCC RST/NMI BSLEN ACLK 8KB Power Management Flash RAM LDO SVM, SVS Brownout PA DVIO VCORE P1.x P2.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com RST/NMI P5.2/XT2IN P5.3/XT2OUT TEST/SBWTCK PJ.0/TDO PJ.1/TDI/TCLK PJ.2/TMS PJ.3/TCK RSTDVCC/SBWTDIO P6.0/CB0 P6.1/CB1 P6.2/CB2 Pin Designation – F5214, F5212 – RGZ Package 48 47 46 45 44 43 42 41 40 39 38 37 P6.3/CB3 1 36 BSLEN P6.4/CB4 2 35 P4.6/PM_NONE P6.5/CB5 3 34 P4.5/PM_UCA1RXD/PM_UCA1SOMI P5.0 4 33 P4.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Pin Designation – F5229, F5227, F5219, F5217 – ZQE Package ZQE PACKAGE (TOP VIEW) P6.0 RSTDVCC PJ.2 TEST RST/NMI P7.5 P7.1 A7 A8 A9 A2 P6.2 P6.1 PJ.3 P5.3 P5.2 B1 B2 B3 B4 B5 P6.4 P6.3 PJ.1 PJ.0 C1 C2 C4 C5 C6 P6.6 P6.5 P6.7 D1 D2 D3 D4 D5 D6 P5.0 P5.1 E1 E2 E3 E4 E5 E6 E7 E8 P5.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com Pin Designation – F5229, F5227, F5219, F5217 – YFF Package YFF PACKAGE (BALL-SIDE VIEW) YFF PACKAGE (TOP VIEW) D H8 P3.0 H7 P3.3 H6 DVSS H5 DVIO H4 P4.1 H3 P4.4 H2 P4.6 H1 P7.0 H1 P7.0 H2 P4.6 H3 P4.4 H4 P4.1 H5 DVIO H6 DVSS H7 P3.3 H8 P3.0 G8 P2.6 G7 P3.1 G6 P3.2 G5 P3.4 G4 P4.3 G3 P4.7 G2 P7.1 G1 P7.3 G1 P7.3 G2 P7.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Table 3. Terminal Functions TERMINAL NAME I/O (1) NO. DESCRIPTION RGC ZQE YFF RGZ P6.4/CB4/A4 5 C1 A2 2 I/O General-purpose digital I/O Comparator_B input CB4 Analog input A4 – ADC (not available on all device types) P6.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com Table 3. Terminal Functions (continued) TERMINAL I/O (1) NO. NAME DESCRIPTION RGC ZQE YFF RGZ P1.4/TA0.3 (4) 22 H4 C5 17 I/O General-purpose digital I/O with port interrupt TA0 CCR3 capture: CCI3A input compare: Out3 output P1.5/TA0.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Table 3. Terminal Functions (continued) TERMINAL I/O (1) NO. NAME RGC ZQE YFF DESCRIPTION RGZ 36 G8 G6 24 I/O General-purpose digital I/O Clock signal input – USCI_B0 SPI slave mode Clock signal output – USCI_B0 SPI master mode Slave transmit enable – USCI_A0 SPI mode P3.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com Table 3. Terminal Functions (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION RGC ZQE YFF RGZ P7.0/TB0.0 (7) 49 B8, B9 H1 N/A I/O General-purpose digital I/O (not available on all device types) TB0 CCR0 capture: CCI0A input, compare: Out0 output (not available on all device types) P7.1/TB0.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Table 3. Terminal Functions (continued) TERMINAL NAME I/O (1) NO. DESCRIPTION RGC ZQE YFF RGZ P6.0/CB0/A0 1 A1 C2 46 I/O General-purpose digital I/O Comparator_B input CB0 Analog input A0 – ADC (not available on all device types) P6.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com Development Tools Support All MSP430™ microcontrollers are supported by a wide variety of software and hardware development tools. Tools are available from TI and various third parties. See them all at www.ti.com/msp430tools. Hardware Features See the Code Composer Studio for MSP430 User's Guide (SLAU157) for details on the available features.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 SYS/BIOS SYS/BIOS is an advanced real-time operating system for the MSP430 microcontrollers. It features preemptive deterministic multi-tasking, hardware abstraction, memory management, and real-time analysis. SYS/BIOS is available free of charge and is provided with full source code.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Short-Form Description CPU (Link to user's guide) The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com Interrupt Vector Addresses The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 4.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Table 4. Interrupt Sources, Flags, and Vectors (continued) (5) INTERRUPT SOURCE INTERRUPT FLAG Reserved Reserved (5) SYSTEM INTERRUPT WORD ADDRESS PRIORITY 0FFD0h 40 ⋮ ⋮ 0FF80h 0, lowest Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com Table 5.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Bootstrap Loader (BSL) The BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the device memory via the BSL is protected by an user-defined password. Because the F522x and F521x have split I/O power domains, it is possible to interface with the BSL from either the DVCC or DVIO supply domains.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com NOTE To invoke the BSL from the DVCC domain, the RSTDVCC/SBWTDIO and TEST/SBWTCK pins must be used for the entry sequence. It is critical not to confuse the RST/NMI pin with the RSTDVCC/SBWTDIO pin. In other MSP430 devices, SBWTDIO is shared with the RST/NMI pin and RSTDVCC does not exist.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Spy-Bi-Wire Interface In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface. SpyBi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire interface pin requirements are shown in Table 9.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com Peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). Digital I/O (Link to user's guide) • All individual I/O bits are independently programmable.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Table 10.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com Power Management Module (PMM) (Link to user's guide) The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor (SVS) and supply voltage monitoring (SVM) circuitry, and brownout protection.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 System Module (SYS) (Link to user's guide) The SYS module handles many of the system functions within the device. These include power-on reset (POR) and power-up clear (PUC) handling, NMI source selection and management, reset interrupt vector generators, bootstrap loader (BSL) entry mechanisms, and configuration management (device descriptors).
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com DMA Controller (Link to user's guide) The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC10_A conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Universal Serial Communication Interface (USCI) (Links to user's guide: UART Mode, SPI Mode, I2C Mode) The USCI modules are used for serial data communication.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com TA0 (Link to user's guide) TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. It can support multiple captures or compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 TA1 (Link to user's guide) TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It can support multiple captures or compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com TA2 (Link to user's guide) TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It can support multiple captures or compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 TB0 (Link to user's guide) TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. It can support multiple captures or compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com Comparator_B (Link to user's guide) The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions, battery voltage supervision, and monitoring of external analog signals. ADC10_A (Link to user's guide) The ADC10_A module supports fast 10-bit analog-to-digital conversions.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Peripheral File Map Table 18.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com Table 19. Special Function Registers (Base Address: 0100h) REGISTER DESCRIPTION REGISTER OFFSET SFR interrupt enable SFRIE1 00h SFR interrupt flag SFRIFG1 02h SFR reset pin control SFRRPCR 04h Table 20.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Table 26.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com Table 29. Port P1, P2 Registers (Base Address: 0200h) (continued) REGISTER DESCRIPTION REGISTER OFFSET Port P2 interrupt vector word P2IV 1Eh Port P2 interrupt edge select P2IES 19h Port P2 interrupt enable P2IE 1Bh Port P2 interrupt flag P2IFG 1Dh Table 30.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Table 33. Port J Registers (Base Address: 0320h) REGISTER DESCRIPTION REGISTER OFFSET Port PJ input PJIN 00h Port PJ output PJOUT 02h Port PJ direction PJDIR 04h Port PJ pullup or pulldown enable PJREN 06h Port PJ drive strength PJDS 08h Table 34.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com Table 36.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Table 39.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com Table 40. DMA Registers (Base Address DMA General Control: 0500h, DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h) (continued) REGISTER DESCRIPTION REGISTER OFFSET DMA module control 2 DMACTL2 04h DMA module control 3 DMACTL3 06h DMA module control 4 DMACTL4 08h DMA interrupt vector DMAIV 0Eh Table 41.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Table 43.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) Voltage applied at VCC to VSS -0.3 V to 4.1 V Voltage applied at VIO to VSS -0.3 V to 2.2 V Voltage applied to any pin (excluding VCORE and VIO pins) (2) -0.3 V to (VCC + 0.3 V) Voltage applied to VIO pins -0.3 V to (VIO + 0.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 VCC VIO VIO,min VSS t VCC ≤ VIO while VIO < VIO,min VIO ≤ VCC VCC ≤ VIO while VIO < VIO,min NOTE: The device supports continuous operation with VCC = VSS while VIO is fully within its specification.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com VCC V(SVSH_+), min tWAKE_UP_RESET tWAKE_UP_RESET DVCC tWAKE_UP_RESET VCC VIT+ RSTDVCC VCC ≥ VRSTDVCC VRSTDVCC = VCC VIO tWAKE_UP_RESET DVIO tWAKE_UP_RESET VIO VIT+ RST VIO ≥ VRST VRST = VIO t NOTE: The device remains in reset based on the conditions of the RSTDVCC and RST pins and the voltage present on DVCC voltage supply.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 25 System Frequency - MHz 3 20 2 2, 3 1 1, 2 1, 2, 3 0, 1 0, 1, 2 0, 1, 2, 3 12 8 0 0 1.8 2.0 2.2 2.4 3.6 Supply Voltage - V The numbers within the fields denote the supported PMMCOREVx settings. Figure 4.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com Electrical Characteristics Active Mode Supply Current Into VCC Excluding External Current over recommended operating free-air temperature (unless otherwise noted) (1) (2) (3) FREQUENCY (fDCO = fMCLK = fSMCLK) PARAMETER EXECUTION MEMORY VCC PMMCOREVx 1 MHz TYP IAM, IAM, (1) (2) (3) 52 Flash RAM Flash RAM 3.0 V 3.0 V MAX 0.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Low-Power Mode Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) PARAMETER ILPM0,1MHz Low-power mode 0 (3) (4) ILPM2 Low-power mode 2 (5) (4) 85°C 0 73 77 91 80 85 97 3.0 V 3 79 83 99 88 95 107 2.2 V 0 6.5 6.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com Schmitt-Trigger Inputs – General-Purpose I/O DVCC Domain (1) (P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Leakage Current – General-Purpose I/O DVCC Domain (P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER Ilkg(Px.y) (1) (2) High-impedance leakage current TEST CONDITIONS (1) (2) VCC MIN MAX 1.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com Outputs – General-Purpose I/O DVIO Domain (Full Drive Strength) (P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Output Frequency – General-Purpose I/O DVCC Domain (P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER Port output frequency (with load) fPx.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 8.0 VCC = 3.0 V Px.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TA = 25°C VCC = 3.0 V Px.y 55.0 50.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com Crystal Oscillator, XT1, Low-Frequency Mode (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1, TA = 25°C ΔIDVCC.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Crystal Oscillator, XT2 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) PARAMETER TEST CONDITIONS VCC MIN fOSC = 4 MHz, XT2OFF = 0, XT2BYPASS = 0, XT2DRIVEx = 0, TA = 25°C IDVCC.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 DCO Frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT fDCO(0,0) DCO frequency (0, 0) DCORSELx = 0, DCOx = 0, MODx = 0 0.07 0.20 MHz fDCO(0,31) DCO frequency (0, 31) (1) DCORSELx = 0, DCOx = 31, MODx = 0 0.70 1.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 PMM, SVS High Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN SVSHE = 0, DVCC = 3.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com PMM, SVM High Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP SVMHE = 0, DVCC = 3.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com Timer_A over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VIO MIN TYP MAX UNIT 1.62 V to 1.8 V 25 Timer_A input clock frequency Internal: SMCLK, ACLK External: TACLK Duty cycle = 50% ± 10% 1.8 V fTA 3.0 V 1.62 V to 1.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tHD,MO tVALID,MO SIMO Figure 14. SPI Master Mode, CKPH = 0 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tHD,MI tSU,MI SOMI tHD,MO tVALID,MO SIMO Figure 15.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 USCI (SPI Slave Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note (1), Figure 16 and Figure 17) PARAMETER TEST CONDITIONS VCC VIO 1.8 V 1.62 V to 1.80 V 12 3.0 V 1.62 V to 1.98 V 12 2.4 V 1.62 V to 1.98 V 10 3.0 V 1.62 V to 1.98 V 10 1.8 V 1.62 V to 1.80 V 6 3.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tSU,SI tLO/HI tHD,SI SIMO tHD,SO tVALID,SO tSTE,ACC tSTE,DIS SOMI Figure 16. SPI Slave Mode, CKPH = 0 tSTE,LAG tSTE,LEAD STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tHD,SI tSU,SI SIMO tSTE,ACC tHD,MO tVALID,SO tSTE,DIS SOMI Figure 17.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 10-Bit ADC, Linearity Parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT EI Integral linearity error 1.4 V ≤ (VeREF+ – VREF–/VeREF–)min ≤ 1.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Comparator_B over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC TEST CONDITIONS VCC MIN Supply voltage TYP 1.8 MAX 3.6 1.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com Flash Memory over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TEST CONDITIONS PARAMETER DVCC(PGM/ERASE) Program and erase supply voltage MIN TYP 1.8 MAX 3.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 DVIO BSL Entry over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC VIO MIN TYP MAX UNIT tSU, BSLEN Setup time BSLEN to RST/NMI (1) 2.2 V, 3 V 1.62 V to 1.98 V 100 ns tHO, Hold time BSLEN to RST/NMI (2) 2.2 V, 3 V 1.62 V to 1.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com INPUT/OUTPUT SCHEMATICS Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger Pad Logic P1REN.x P1DIR.x 0 From module 1 P1OUT.x 0 From module 1 0 (P1.0 to P1.3) DVCC (P1.4 to P1.7) DVIO 1 1 Direction 0: Input 1: Output P1DS.x 0: Low drive 1: High drive P1SEL.x P1IN.x EN To module DVSS P1.0/TA0CLK/ACLK P1.1/TA0.0 P1.2/TA0.1 P1.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Table 47. Port P1 (P1.0 to P1.7) Pin Functions PIN NAME (P1.x) P1.0/TA0CLK/ACLK P1.1/TA0.0 P1.2/TA0.1 P1.3/TA0.2 P1.4/TA0.3 x 0 1 2 3 4 FUNCTION P1DIR.x P1SEL.x P1.0 (I/O) I: 0; O: 1 0 TA0CLK 0 1 ACLK 1 1 I: 0; O: 1 0 TA0.CCI0A 0 1 TA0.0 1 1 I: 0; O: 1 0 TA0.CCI1A 0 1 TA0.1 1 1 I: 0; O: 1 0 TA0.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger Pad Logic P2REN.x P2DIR.x 0 From module 1 P2OUT.x 0 From module 1 0 DVIO 1 1 Direction 0: Input 1: Output P2DS.x 0: Low drive 1: High drive P2SEL.x P2IN.x EN To module DVSS P2.0/TA1.1 P2.1/TA1.2 P2.2/TA2CLK/SMCLK P2.3/TA2.0 P2.4/TA2.1 P2.5/TA2.2 P2.6/RTCCLK/DMAE0 P2.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Table 48. Port P2 (P2.0 to P2.7) Pin Functions PIN NAME (P2.x) P2.0/TA1.1 P2.1/TA1.2 (2) 0 (2) P2.2/TA2CLK/SMCLK x 1 (2) P2.3/TA2.0 (2) P2.4/TA2.1 (2) P2.5/TA2.2 (2) P2.6/RTCCLK/DMAE0 (2) 2 3 4 5 6 FUNCTION P2.0 (I/O) 7 P2SEL.x I: 0; O: 1 0 0 1 TA1.1 1 1 P2.1 (I/O) I: 0; O: 1 0 TA1.CCI2A 0 1 TA1.2 1 1 P2.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com Port P3, P3.0 to P3.4, Input/Output With Schmitt Trigger Pad Logic P3REN.x P3DIR.x 0 From module 1 P3OUT.x 0 From module 1 DVSS 0 DVIO 1 1 Direction 0: Input 1: Output P3DS.x 0: Low drive 1: High drive P3SEL.x P3IN.x P3.0/UCB0SIMO/UCB0SDA P3.1/UCB0SOMI/UCB0SCL P3.2/UCB0CLK/UCA0STE P3.3/UCA0TXD/UCA0SIMO P3.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger Pad Logic P4REN.x P4DIR.x 0 from Port Mapping Control 1 P4OUT.x 0 from Port Mapping Control 1 DVSS 0 DVIO 1 1 Direction 0: Input 1: Output P4.0/P4MAP0 P4.1/P4MAP1 P4.2/P4MAP2 P4.3/P4MAP3 P4.4/P4MAP4 P4.5/P4MAP5 P4.6/P4MAP6 P4.7/P4MAP7 P4DS.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger Pad Logic to/from Reference (n/a MSP430F521x) (n/a MSPF430F521x) to ADC10 (n/a MSPF430F521x) INCHx = x P5REN.x P5DIR.x DVSS 0 DVCC 1 1 0 1 P5OUT.x 0 From module 1 P5.0/(A8/VeREF+) P5.1/(A9/VeREF–) P5DS.x 0: Low drive 1: High drive P5SEL.x P5IN.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Port P5, P5.2, Input/Output With Schmitt Trigger Pad Logic To XT2 P5REN.2 P5DIR.2 DVSS 0 DVCC 1 1 0 1 P5OUT.2 0 Module X OUT 1 P5DS.2 0: Low drive 1: High drive P5SEL.2 P5.2/XT2IN P5IN.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com Port P5, P5.3, Input/Output With Schmitt Trigger Pad Logic To XT2 P5REN.3 P5DIR.3 DVSS 0 DVCC 1 1 0 1 P5OUT.3 0 Module X OUT 1 P5.3/XT2OUT P5DS.3 0: Low drive 1: High drive P5SEL.3 P5IN.3 Bus Keeper EN Module X IN D Table 52. Port P5 (P5.2, P5.3) Pin Functions PIN NAME (P5.x) P5.2/XT2IN P5.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Port P5, P5.4 and P5.5 Input/Output With Schmitt Trigger Pad Logic to XT1 P5REN.4 P5DIR.4 DVSS 0 DVCC 1 1 0 1 P5OUT.4 0 Module X OUT 1 P5DS.4 0: Low drive 1: High drive P5SEL.4 P5.4/XIN P5IN.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com Pad Logic to XT1 P5REN.5 P5DIR.5 DVSS 0 DVCC 1 1 0 1 P5OUT.5 0 Module X OUT 1 P5.5/XOUT P5DS.5 0: Low drive 1: High drive P5SEL.5 XT1BYPASS P5IN.5 Bus Keeper EN Module X IN D Table 53. Port P5 (P5.4 and P5.5) Pin Functions PIN NAME (P5.x) P5.4/XIN x 4 FUNCTION P5DIR.x P5SEL.4 P5SEL.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger Pad Logic to ADC10 (n/a MSPF430F521x) INCHx = x (n/a MSPF430F521x) to Comparator_B from Comparator_B CBPD.x P6REN.x P6DIR.x 0 0 From module 1 0 DVCC 1 P6DS.x 0: Low drive 1: High drive P6SEL.x P6IN.x EN To module 1 Direction 0: Input 1: Output 1 P6OUT.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com Table 54. Port P6 (P6.0 to P6.7) Pin Functions PIN NAME (P6.x) P6.0/CB0/(A0) x 0 FUNCTION P6.0 (I/O) A0 CB0 (1) P6.1/CB1/(A1) 1 P6.2/CB2/(A2) 2 P6.3/CB3/(A3) 3 P6.4/CB4/(A4) 4 P6.1 (I/O) 6 (1) (2) 92 7 X X X 1 I: 0; O: 1 0 0 1 X 1 I: 0; O: 1 0 0 P6.2 (I/O) A2 X 1 X CB2 (1) X X 1 I: 0; O: 1 0 0 P6.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Port P7, P7.0 to P7.5, Input/Output With Schmitt Trigger Pad Logic P7REN.x P7DIR.x 0 From module 1 P7OUT.x 0 DVSS 0 DVIO 1 1 Direction 0: Input 1: Output 1 P7.0/TB0.0 P7.1/TB0.1 P7.2/TB0.2 P7.3/TB0.3 P7.4/TB0.4 P7.5/TB0.5 P7DS.x 0: Low drive 1: High drive P7SEL.x P7IN.x EN D To module Table 55. Port P7 (P7.0 to P7.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com Port J, J.0 JTAG pin TDO, Input/Output With Schmitt Trigger or Output Pad Logic PJREN.0 PJDIR.0 0 DVCC 1 PJOUT.0 0 From JTAG 1 DVSS 0 DVCC 1 1 PJ.0/TDO PJDS.0 0: Low drive 1: High drive From JTAG PJIN.0 EN D Port J, J.1 to J.3 JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output Pad Logic PJREN.x PJDIR.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Table 56. Port PJ (PJ.0 to PJ.3) Pin Functions PIN NAME (PJ.x) x CONTROL BITS AND SIGNALS (1) FUNCTION PJDIR.x PJ.0/TDO 0 (2) I: 0; O: 1 PJ.1 (I/O) (2) I: 0; O: 1 PJ.0 (I/O) TDO (3) PJ.1/TDI/TCLK 1 X TDI/TCLK (3) PJ.2/TMS 2 PJ.2 (I/O) TMS (3) PJ.3/TCK 3 (1) (2) (3) (4) X I: 0; O: 1 (4) PJ.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com DEVICE DESCRIPTORS Table 57 and Table 58 list the complete contents of the device descriptor tag-length-value (TLV) structure for each device type. Table 57.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Table 57.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com Table 57.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Table 58.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com Table 58.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 www.ti.com SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 Table 58.
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222 MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212 SLAS718D – NOVEMBER 2012 – REVISED OCTOBER 2013 www.ti.com REVISION HISTORY REVISION SLAS718 DESCRIPTION Initial release SLAS718A DCO Frequency, Added note (1). SLAS718B Pin Designation – F5229, F5227, F5219, F5217 – YFF Package, Added ball-side view and changed orientation of topside view. REF, External Reference, Changed note (1) (changed from "12-bit accuracy" to "10-bit accuracy").
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 26-Feb-2014 Status (1) MSP430F5229IZQER ACTIVE Package Type Package Pins Package Drawing Qty BGA MICROSTAR JUNIOR ZQE 80 2500 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR Op Temp (°C) Device Marking (4/5) F5229 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
PACKAGE MATERIALS INFORMATION www.ti.com 1-Apr-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant MSP430F5212IRGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 MSP430F5214IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 MSP430F5214IRGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 1-Apr-2014 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant MSP430F5222IRGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 MSP430F5224IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 MSP430F5224IRGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 MSP430F5227IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.
PACKAGE MATERIALS INFORMATION www.ti.com 1-Apr-2014 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430F5212IRGZT VQFN RGZ 48 250 210.0 185.0 35.0 MSP430F5214IRGZR VQFN RGZ 48 2500 367.0 367.0 38.0 MSP430F5214IRGZT VQFN RGZ 48 250 210.0 185.0 35.0 MSP430F5217IRGCR VQFN RGC 64 2000 367.0 367.0 38.0 MSP430F5217IRGCT VQFN RGC 64 250 210.0 185.0 35.0 MSP430F5217IYFFR DSBGA YFF 64 2500 367.0 367.0 35.
D: Max = 3.565 mm, Min =3.505 mm E: Max = 3.445 mm, Min =3.
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