Datasheet

SDA
SCL
t
HD,DAT
t
SU,DAT
t
HD,STA
t
HIGH
t
LOW
t
BUF
t
HD,STA
t
SU,STA
t
SP
t
SU,STO
ECCN 5E002 TSPA - Technology / Software Publicly Available
MSP430F677x , MSP430F676x , MSP430F674x
www.ti.com SLAS768D –SEPTEMBER 2012–REVISED DECEMBER 2013
eUSCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 17)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
Internal: SMCLK, ACLK
f
eUSCI
eUSCI input clock frequency External: UCLK f
SYSTEM
MHz
Duty cycle = 50% ± 10%
f
SCL
SCL clock frequency 2 V, 3 V 0 400 kHz
f
SCL
= 100 kHz 5.1
t
HD,STA
Hold time (repeated) START 2 V, 3 V µs
f
SCL
> 100 kHz 1.5
f
SCL
= 100 kHz 5.1
t
SU,STA
Setup time for a repeated START 2 V, 3 V µs
f
SCL
> 100 kHz 1.4
t
HD,DAT
Data hold time 2 V, 3 V 0.4 µs
f
SCL
= 100 kHz 5.0
t
SU,DAT
Data setup time 2 V, 3 V µs
f
SCL
> 100 kHz 1.3
f
SCL
= 100 kHz 5.2
t
SU,STO
Setup time for STOP 2 V, 3 V µs
f
SCL
> 100 kHz 1.7
UCGLITx = 0 75 220 ns
UCGLITx = 1 35 120 ns
Pulse duration of spikes suppressed by input
t
SP
2 V, 3 V
filter
UCGLITx = 2 30 60 ns
UCGLITx = 3 20 35 ns
UCCLTOx = 1 30 ms
t
TIMEOUT
Clock low timeout UCCLTOx = 2 2 V, 3 V 33 ms
UCCLTOx = 3 37 ms
Figure 17. I2C Mode Timing
Schmitt-Trigger Inputs – RTC Tamper Detect Pin
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS AUXVCC3 MIN TYP MAX UNIT
1.8 V 0.80 1.40
V
IT+
Positive-going input threshold voltage V
3 V 1.50 2.10
1.8 V 0.45 1.00
V
IT–
Negative-going input threshold voltage V
3 V 0.75 1.65
1.8 V 0.3 0.85
V
hys
Input voltage hysteresis (V
IT+
– V
IT–
) V
3 V 0.4 1.0
For pullup: V
IN
= V
SS
R
Pull
Pullup or pulldown resistor For pulldown: V
IN
= 20 35 50 kΩ
AUXVCC3
C
I
Input capacitance V
IN
= V
SS
or AUXVCC3 5 pF
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