Datasheet

t
SU,MI
t
HD,MI
UCLK
SOMI
SIMO
t
VALID,MO
CKPL =0
CKPL =1
t
LOW/HIGH
t
LOW/HIGH
1/f
UCxCLK
t
STE,LEAD
t
STE,LAG
t
STE,ACC
t
STE,DIS
UCMODEx=01
UCMODEx=10
STE
ECCN 5E002 TSPA - Technology / Software Publicly Available
MSP430F677x , MSP430F676x , MSP430F674x
www.ti.com SLAS768D –SEPTEMBER 2012–REVISED DECEMBER 2013
Figure 14. SPI Master Mode, CKPH = 1
eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
2 V 4
t
STE,LEAD
STE lead time, STE low to clock ns
3 V 3
2 V 0
t
STE,LAG
STE lag time, Last clock to STE high ns
3 V 0
2 V 46
t
STE,ACC
STE access time, STE low to SOMI data out ns
3 V 24
2 V 38
STE disable time, STE high to SOMI high
t
STE,DIS
ns
impedance
3 V 25
2 V 2
t
SU,SI
SIMO input data setup time ns
3 V 1
2 V 2
t
HD,SI
SIMO input data hold time ns
3 V 2
2 V 55
UCLK edge to SOMI valid,
t
VALID,SO
SOMI output data valid time
(2)
ns
C
L
= 20 pF
3 V 32
2 V 24
t
HD,SO
SOMI output data hold time
(3)
C
L
= 20 pF ns
3 V 16
(1) f
UCxCLK
= 1/2t
LO/HI
with t
LO/HI
≥ max(t
VALID,MO(Master)
+ t
SU,SI(eUSCI)
, t
SU,MI(Master)
+ t
VALID,SO(eUSCI)
).
For the master's parameters t
SU,MI(Master)
and t
VALID,MO(Master)
refer to the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 15 and Figure 16.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 15
and Figure 16.
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