Datasheet

t
SU,MI
t
HD,MI
UCLK
SOMI
SIMO
t
VALID,MO
CKPL =0
CKPL =1
t
LOW/HIGH
t
LOW/HIGH
1/f
UCxCLK
STE
t
STE,LEAD
t
STE,LAG
t
STE,ACC
t
STE,DIS
UCMODEx=01
UCMODEx=10
ECCN 5E002 TSPA - Technology / Software Publicly Available
MSP430F677x , MSP430F676x , MSP430F674x
SLAS768D –SEPTEMBER 2012–REVISED DECEMBER 2013 www.ti.com
eUSCI (SPI Master Mode) (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
2 V 0
t
HD,MI
SOMI input data hold time ns
3 V 0
2 V 9
UCLK edge to SIMO valid,
t
VALID,MO
SIMO output data valid time
(2)
ns
C
L
= 20 pF
3 V 5
2 V 0
t
HD,MO
SIMO output data hold time
(3)
C
L
= 20 pF ns
3 V 0
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 13 and Figure 14.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in
Figure 13 and Figure 14.
Figure 13. SPI Master Mode, CKPH = 0
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