Datasheet

ECCN 5E002 TSPA - Technology / Software Publicly Available
MSP430F677x , MSP430F676x , MSP430F674x
www.ti.com SLAS768D –SEPTEMBER 2012–REVISED DECEMBER 2013
Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
Internal: SMCLK or ACLK,
f
TA
Timer_A input clock frequency External: TACLK, 1.8 V, 3 V 25 MHz
Duty cycle = 50% ± 10%
All capture inputs.
t
TA,cap
Timer_A capture timing Minimum pulse duration required for 1.8 V, 3 V 20 ns
capture.
eUSCI (UART Mode) Recommended Operating Conditions
PARAMETER CONDITIONS V
CC
MIN TYP MAX UNIT
Internal: SMCLK or ACLK,
f
eUSCI
eUSCI input clock frequency External: UCLK, f
SYSTEM
MHz
Duty cycle = 50% ± 10%
BITCLK clock frequency
f
BITCLK
5 MHz
(equals baud rate in MBaud)
eUSCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
UCGLITx = 0 10 15 25
UCGLITx = 1 30 50 85
t
t
UART receive deglitch time
(1)
2 V, 3 V ns
UCGLITx = 2 50 80 150
UCGLITx = 3 70 120 200
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To make sure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
eUSCI (SPI Master Mode) Recommended Operating Conditions
PARAMETER CONDITIONS V
CC
MIN TYP MAX UNIT
Internal: SMCLK or ACLK,
f
eUSCI
eUSCI input clock frequency f
SYSTEM
MHz
Duty cycle = 50% ± 10%
eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
UCSTEM = 0, UCMODEx = 01 or 10 2 V, 3 V 150
t
STE,LEAD
STE lead time, STE low to clock ns
UCSTEM = 1, UCMODEx = 01 or 10 2 V, 3 V 150
UCSTEM = 0, UCMODEx = 01 or 10 2 V, 3 V 200
STE lag time, Last clock to STE
t
STE,LAG
ns
high
UCSTEM = 1, UCMODEx = 01 or 10 2 V, 3 V 200
2 V 50
UCSTEM = 0, UCMODEx = 01 or 10
3V 30
STE access time, STE low to
t
STE,ACC
ns
SIMO data out
2 V 50
UCSTEM = 1, UCMODEx = 01 or 10
3 V 30
2 V 40
UCSTEM = 0, UCMODEx = 01 or 10
3V 25
STE disable time, STE high to
t
STE,DIS
ns
SIMO high impedance
2 V 40
UCSTEM = 1, UCMODEx = 01 or 10
3 V 25
2 V 50
t
SU,MI
SOMI input data setup time ns
3 V 30
(1) f
UCxCLK
= 1/2t
LO/HI
with t
LO/HI
= max(t
VALID,MO(eUSCI)
+ t
SU,SI(Slave)
, t
SU,MI(eUSCI)
+ t
VALID,SO(Slave)
).
For the slave's parameters t
SU,SI(Slave)
and t
VALID,SO(Slave)
see the SPI parameters of the attached slave.
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