Datasheet

PEU PACKAGE
1
XIN
2XOUT
3AUXVCC3
4RTCCAP1
5RTCCAP0
6P1.5/SMCLK/CB0/A5
7P1.4/MCLK/CB1/A4
8P1.3/ADC10CLK/A3
9P1.2/ACLK/A2
10P1.1/TA2.1/VeREF+/A1
11P1.0/TA1.1/VeREF-/A0
12P2.4/PM_TA2.0
13P2.5/PM_UCB0SOMI/PM_UCB0SCL
14P2.6/PM_UCB0SIMO/PM_UCB0SDA
15P2.7/PM_UCB0CLK
16P3.0/PM_UCA0RXD/PM_UCA0SOMI
17P3.1/PM_UCA0TXD/PM_UCA0SIMO
18P3.2/PM_UCA0CLK
19P3.3/PM_UCA1CLK
20P3.4/PM_UCA1RXD/PM_UCA1SOMI
21P3.5/PM_UCA1TXD/PM_UCA1SIMO
22COM0
23COM1
24P1.6/COM2
25P1.7/COM3
39
P4.1/PM_UCA3RXD/M_UCA3SOMI
40
P4.2/PM_UCA3TXD/PM_UCA3SIMO
41
P4.3/PM_UCA3CLK
42
P4.4/PM_UCB1SOMI/PM_UCB1SCL
43
P4.5/PM_UCB1SIMO/PM_UCB1SDA
44
P4.6/PM_UCB1CLK
45
P4.7/PM_TA3.0
46
P6.1/SD4DIO/S39
47
P6.2/SD5DIOS38
48
P6.3/SD6DIO/S37
49
P6.4/S36
50
P6.5/S35
51
P6.6/S34
52
P6.7/S33
53
P7.0/S32
54
P7.1/S31
55
P7.2/S30
56
P7.3/S29
57
P7.4/S28
58
P7.5/S27
59
P7.6/S26
60
P7.7/S25
61
P8.0/S24
62
P8.1/S23
63
P8.2/S22
78 P9.7/S9
79 P10.0/S8
80 P10.1/S7
81 P10.2/S6
82 P10.3/S5
83 P10.4/S4
84 P10.5/S3
85 P10.6/S2
86 P10.7/S1
87 P11.0/S0
88 P11.1/TA3.1/CB3
89 P11.2/TA1.1
90 P11.3/TA2.1
91 P11.4/CBOUT
92 P11.5/TACLK/RTCCLK
93 P2.0/PM_TA0.0/BSL_TX
94
P2.1/PM_TA0.1/BSL_RX
95 P2.2/PM_TA0.2
96 P2.3/PM_TA1.0
97 TEST/SBWTCK
98 PJ.0/TDO
99 PJ.1/TDI/TCLK
100 PJ.2/TMS
101 PJ.3/TCK
102 RST/NMI/SBWTDIO
104
SD0N0
105
SD1P0
106
SD1N0
107
SD2P0
108
SD2N0
109
SD3P0
110
SD3N0
111
VASYS2
112
AVSS2
113
VREF
114
SD4P0
115
SD4N0
116
SD5P0
117
SD5N0
118
SD6P0
119
SD6N0
120
AVSS1
121
AVCC
122
VASYS1
123
AUXVCC2
124
AUXVCC1
125
VDSYS1
126
DVCC
127
DVSS1
128
VCORE
26P5.0/COM4
27P5.1/COM5
28P5.2/COM6
29P5.3/COM7
30
LCDCAP/R33
31P5.4/SDCLK/R23
32P5.5/SD0DIO/LCDREF/R13
33P5.6/SD1DIO/R03
34P5.7/SD2DIO/CB2
35P6.0/SD3DIO
36P3.6/PM_UCA2RXD/PM_UCA2SOMI
37P3.7/PM_UCA2TXD/PM_UCA2SIMO
38P4.0/PM_UCA2CLK
64
P8.3/S21
103
SD0P0
65 P8.4/S20
66 P8.5/S19
67 P8.6/S18
68 P8.7/S17
69 VDSYS2
70 DVSS2
71 P9.0/S16
72 P9.1/S15
73 P9.2/S14
74 P9.3/S13
75 P9.4/S12
76 P9.5/S11
77 P9.6/S10
ECCN 5E002 TSPA - Technology / Software Publicly Available
MSP430F677x , MSP430F676x , MSP430F674x
SLAS768D –SEPTEMBER 2012–REVISED DECEMBER 2013 www.ti.com
Pin Designation, MSP430F677xIPEU
A. The secondary digital functions on Ports P2, P3 and P4 are fully mappable. The pin designation shows only the
default mapping. See Table 15 for details.
B. The pair of pins VDSYS1 and VDSYS2, VASYS1 and VASYS2 must be connected externally on board for proper
device operation.
C. CAUTION: The LCDCAP/R33 pin must be connected to DVSS if it is not used.
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