Datasheet
ECCN 5E002 TSPA - Technology / Software Publicly Available
MSP430F677x
,
MSP430F676x
,
MSP430F674x
www.ti.com
SLAS768D –SEPTEMBER 2012–REVISED DECEMBER 2013
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
Voltage applied at DVCC to DVSS –0.3 V to 4.1 V
Voltage applied to any pin (excluding VCORE)
(2)
–0.3 V to V
CC
+ 0.3 V
Diode current at any device pin ±2 mA
Storage temperature range, T
stg
(3)
–55°C to 105°C
Maximum junction temperature, T
J
95°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to V
SS
. V
CORE
is for internal device use only. No external DC loading or voltage should be applied.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Recommended Operating Conditions
Typical values are specified at V
CC
= 3.3 V and T
A
= 25°C (unless otherwise noted)
MIN NOM MAX UNIT
PMMCOREVx = 0 1.8 3.6 V
PMMCOREVx = 0, 1 2.0 3.6 V
Supply voltage during program execution and flash
V
CC
programming. V
AVCC
= V
DVCC
= V
CC
(1)(2)
PMMCOREVx = 0, 1, 2 2.2 3.6 V
PMMCOREVx = 0, 1, 2, 3 2.4 3.6 V
V
SS
Supply voltage V
AVSS
= V
DVSS
= V
SS
0 V
T
A
Operating free-air temperature I version –40 85 °C
T
J
Operating junction temperature I version –40 85 °C
C
VCORE
Recommended capacitor at VCORE 470 nF
C
DVCC
/
Capacitor ratio of DVCC to VCORE 10
C
VCORE
PMMCOREVx = 0,
1.8 V ≤ V
CC
≤ 3.6 V 0 8.0
(default condition)
PMMCOREVx = 1,
0 12.0
Processor frequency (maximum MCLK frequency)
(3) (4)
2 V ≤ V
CC
≤ 3.6 V
f
SYSTEM
MHz
(see Figure 3)
PMMCOREVx = 2,
0 20.0
2.2 V ≤ V
CC
≤ 3.6 V
PMMCOREVx = 3,
0 25.0
2.4 V ≤ V
CC
≤ 3.6 V
I
LOAD,
Maximum load current that can be drawn from DVCC
20 mA
DVCCD
for core and IO (I
LOAD
= I
CORE
+ I
IO
)
I
LOAD,
Maximum load current that can be drawn from
20 mA
AUX1D
AUXVCC1 for core and IO (I
LOAD
= I
CORE
+ I
IO
)
I
LOAD,
Maximum load current that can be drawn from
20 mA
AUX2D
AUXVCC2 for core and IO (I
LOAD
= I
CORE
+ I
IO
)
I
LOAD,
Maximum load current that can be drawn from AVCC
10 mA
AVCCA
for analog modules (I
LOAD
= I
Modules
)
I
LOAD,
Maximum load current that can be drawn from
5 mA
AUX1A
AUXVCC1 for analog modules (I
LOAD
= I
Modules
)
I
LOAD,
Maximum load current that can be drawn from
5 mA
AUX2A
AUXVCC2 for analog modules (I
LOAD
= I
Modules
)
P
INT
Internal power dissipation V
CC
x I(DVCC) W
(1) It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between V(AVCC) and V(DVCC)
can be tolerated during power up and operation.
(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the PMM, SVS High Side threshold
parameters for the exact values and further details.
(3) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the
specified maximum frequency.
(4) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
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