Datasheet

ECCN 5E002 TSPA - Technology / Software Publicly Available
MSP430F677x , MSP430F676x , MSP430F674x
www.ti.com SLAS768D –SEPTEMBER 2012–REVISED DECEMBER 2013
Table 62. eUSCI_B1 Registers (Base Address: 0680h)
REGISTER DESCRIPTION REGISTER OFFSET
USCI_B control word 0 UCB0CTLW0 00h
USCI_B control word 1 UCB0CTLW1 02h
USCI_B bit rate 0 UCB0BR0 06h
USCI_B bit rate 1 UCB0BR1 07h
USCI_B status word UCB0STATW 08h
USCI_B byte counter threshold UCB0TBCNT 0Ah
USCI_B receive buffer UCB0RXBUF 0Ch
USCI_B transmit buffer UCB0TXBUF 0Eh
USCI_B I2C own address 0 UCB0I2COA0 14h
USCI_B I2C own address 1 UCB0I2COA1 16h
USCI_B I2C own address 2 UCB0I2COA2 18h
USCI_B I2C own address 3 UCB0I2COA3 1Ah
USCI_B received address UCB0ADDRX 1Ch
USCI_B address mask UCB0ADDMASK 1Eh
USCI I2C slave address UCB0I2CSA 20h
USCI interrupt enable UCB0IE 2Ah
USCI interrupt flags UCB0IFG 2Ch
USCI interrupt vector word UCB0IV 2Eh
Table 63. ADC10_A Registers (Base Address: 0740h)
REGISTER DESCRIPTION REGISTER OFFSET
ADC10_A Control register 0 ADC10CTL0 00h
ADC10_A Control register 1 ADC10CTL1 02h
ADC10_A Control register 2 ADC10CTL2 04h
ADC10_A Window Comparator Low Threshold ADC10LO 06h
ADC10_A Window Comparator High Threshold ADC10HI 08h
ADC10_A Memory Control Register 0 ADC10MCTL0 0Ah
ADC10_A Conversion Memory Register ADC10MCTL0 12h
ADC10_A Interrupt Enable ADC10IE 1Ah
ADC10_A Interrupt Flags ADC10IGH 1Ch
ADC10_A Interrupt Vector Word ADC10IV 1Eh
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