Datasheet

ECCN 5E002 TSPA - Technology / Software Publicly Available
MSP430F677x , MSP430F676x , MSP430F674x
SLAS768D –SEPTEMBER 2012–REVISED DECEMBER 2013 www.ti.com
Table 55. DMA Channel 1 Registers (Base Address: 0500h)
REGISTER DESCRIPTION REGISTER OFFSET
DMA channel 1 control DMA1CTL 20h
DMA channel 1 source address low DMA1SAL 22h
DMA channel 1 source address high DMA1SAH 24h
DMA channel 1 destination address low DMA1DAL 26h
DMA channel 1 destination address high DMA1DAH 28h
DMA channel 1 transfer size DMA1SZ 2Ah
Table 56. DMA Channel 2 Registers (Base Address: 0500h)
REGISTER DESCRIPTION REGISTER OFFSET
DMA channel 2 control DMA2CTL 30h
DMA channel 2 source address low DMA2SAL 32h
DMA channel 2 source address high DMA2SAH 34h
DMA channel 2 destination address low DMA2DAL 36h
DMA channel 2 destination address high DMA2DAH 38h
DMA channel 2 transfer size DMA2SZ 3Ah
Table 57. eUSCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION REGISTER OFFSET
USCI_A control word 0 UCA0CTLW0 00h
USCI _A control word 1 UCA0CTLW1 02h
USCI_A baud rate 0 UCA0BR0 06h
USCI_A baud rate 1 UCA0BR1 07h
USCI_A modulation control UCA0MCTLW 08h
USCI_A status UCA0STAT 0Ah
USCI_A receive buffer UCA0RXBUF 0Ch
USCI_A transmit buffer UCA0TXBUF 0Eh
USCI_A LIN control UCA0ABCTL 10h
USCI_A IrDA transmit control UCA0IRTCTL 12h
USCI_A IrDA receive control UCA0IRRCTL 13h
USCI_A interrupt enable UCA0IE 1Ah
USCI_A interrupt flags UCA0IFG 1Ch
USCI_A interrupt vector word UCA0IV 1Eh
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