Datasheet

ECCN 5E002 TSPA - Technology / Software Publicly Available

MSP430F677x

MSP430F676x

MSP430F674x

www.ti.com

SLAS768D –SEPTEMBER 2012–REVISED DECEMBER 2013

Table 52. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)

16-bit operand 1 – multiply MPY 00h

16-bit operand 1 – signed multiply MPYS 02h

16-bit operand 1 – multiply accumulate MAC 04h

16-bit operand 1 – signed multiply accumulate MACS 06h

16-bit operand 2 OP2 08h

16 × 16 result low word RESLO 0Ah

16 × 16 result high word RESHI 0Ch

16 × 16 sum extension register SUMEXT 0Eh

32-bit operand 1 – multiply low word MPY32L 10h

32-bit operand 1 – multiply high word MPY32H 12h

32-bit operand 1 – signed multiply low word MPYS32L 14h

32-bit operand 1 – signed multiply high word MPYS32H 16h

32-bit operand 1 – multiply accumulate low word MAC32L 18h

32-bit operand 1 – multiply accumulate high word MAC32H 1Ah

32-bit operand 1 – signed multiply accumulate low word MACS32L 1Ch

32-bit operand 1 – signed multiply accumulate high word MACS32H 1Eh

32-bit operand 2 – low word OP2L 20h

32-bit operand 2 – high word OP2H 22h

32 × 32 result 0 – least significant word RES0 24h

32 × 32 result 1 RES1 26h

32 × 32 result 2 RES2 28h

32 × 32 result 3 – most significant word RES3 2Ah

MPY32 control register 0 MPY32CTL0 2Ch

Table 53. DMA General Control Registers (Base Address: 0500h)

DMA module control 0 DMACTL0 00h

DMA module control 1 DMACTL1 02h

DMA module control 2 DMACTL2 04h

DMA module control 3 DMACTL3 06h

DMA module control 4 DMACTL4 08h

DMA interrupt vector DMAIV 0Eh

Table 54. DMA Channel 0 Registers (Base Address: 0500h)

DMA channel 0 control DMA0CTL 10h

DMA channel 0 source address low DMA0SAL 12h

DMA channel 0 source address high DMA0SAH 14h

DMA channel 0 destination address low DMA0DAL 16h

DMA channel 0 destination address high DMA0DAH 18h

DMA channel 0 transfer size DMA0SZ 1Ah