Datasheet
Unified
Clock
System
512kB
256kB
128kB
Flash
MCLK
ACLK
SMCLK
CPUXV2
and
Working
Registers
(25MHz)
EEM
(S: 8+2)
XIN
XOUT
JTAG/
SBW
Interface/
Port PJ
eUSCI_A0
eUSCI_A1
eUSCI_A2
eUSCI_A3
(UART,
IrDA,SPI)
SD24_B
7 Channel
6 Channel
4 Channel
ADC10_A
10 Bit
200 KSPS
LCD_C
8MUX
Up to 320
Segments
REF
Reference
1.5V, 2.0V,
2.5V
DVCC DVSS AVCC AVSS
PA
I/O Ports
P1/P2
2×8 I/Os
Interrupt
& Wakeup
PA
1×16 I/Os
P1.x
P2.x
RST/NMI
32kB
16kB
RAM
PJ.x
DMA
3 Channel
PMM
Auxiliary
Supplies
LDO
SVM/SVS
BOR
MPY32
SYS
Watchdog
Port
Mapping
Controller
CRC16
PD
I/O Ports
P7/P8
1×8 I/Os
1
PD
1×10 I/Os
×2 I/Os
P7.x
P8.x
PC
I/O Ports
P5/P6
2×8 I/Os
PC
1×16 I/Os
P5.x
P6.x
PB
I/O Ports
P3/P4
2×8 I/Os
PB
1×16 I/Os
P3.x
P4.x
eUSCI_B0
eUSCI_B1
(SPI, I2C)
RTC_CE
(32kHz)
AUX1
AUX2 AUX3
TA1
TA2
TA3
Timer_A
2 CC
Registers
Ta0
Timer_A
3 CC
Registers
AES128
COMP_B
(External
Voltage
Monitoring)
Unified
Clock
System
512kB
256kB
128kB
Flash
MCLK
ACLK
SMCLK
CPUXV2
and
Working
Registers
(25MHz)
EEM
(S: 8+2)
XIN
XOUT
JTAG/
SBW
Interface/
Port PJ
eUSCI_A0
eUSCI_A1
eUSCI_A2
eUSCI_A3
(UART,
IrDA,SPI)
SD24_B
7 Channel
6 Channel
4 Channel
ADC10_A
10 Bit
200 KSPS
LCD_C
8MUX
Up to 320
Segments
REF
Reference
1.5V, 2.0V,
2.5V
DVCC DVSS AVCC AVSS
PA
I/O Ports
P1/P2
2×8 I/Os
Interrupt
& Wakeup
PA
1×16 I/Os
P1.x
P2.x
RST/NMI
32kB
16kB
RAM
PJ.x
DMA
3 Channel
PMM
Auxiliary
Supplies
LDO
SVM/SVS
BOR
MPY32
SYS
Watchdog
Port
Mapping
Controller
CRC16
PD
I/O Ports
P7/P8
2×8 I/Os
PD
1×16 I/Os
I/O Ports
P9/P10
2×8 I/O
PE
1×16 I/O
P7.x
P8.x
PC
I/O Ports
P5/P6
2×8 I/Os
PC
1×16 I/Os
P5.x
P6.x
PB
I/O Ports
P3/P4
2×8 I/Os
PB
1×16 I/Os
P3.x
P4.x
eUSCI_B0
eUSCI_B1
(SPI, I2C)
RTC_CE
(32kHz)
AUX1
AUX2 AUX3
TA1
TA2
TA3
Timer_A
2 CC
Registers
Ta0
Timer_A
3 CC
Registers
AES128
COMP_B
(External
Voltage
Monitoring)
I/O Ports
P11
1×6 I/O
PF
1×6 I/O
PF
P9.x
P10.x
PE
P11.x
ECCN 5E002 TSPA - Technology / Software Publicly Available
MSP430F677x
,
MSP430F676x
,
MSP430F674x
www.ti.com
SLAS768D –SEPTEMBER 2012–REVISED DECEMBER 2013
Functional Block Diagram – MSP430F677xIPEU, MSP430F676xIPEU, and MSP430F674xIPEU
Functional Block Diagram – MSP430F677xIPZ, MSP430F676xIPZ, and MSP430F674xIPZ
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 5