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ECCN 5E002 TSPA - Technology / Software Publicly Available

MSP430F677x

MSP430F676x

MSP430F674x

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SLAS768D –SEPTEMBER 2012–REVISED DECEMBER 2013

Table 15. Port Mapping Mnemonics and Functions (continued)

VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION

12 PM_UCA2STE eUSCI_A2 SPI slave transmit enable (direction controlled by eUSCI)

PM_UCA3RXD eUSCI_A3 UART RXD (direction controlled by eUSCI – Input)

PM_UCA3SOMI eUSCI_A3 SPI slave out master in (direction controlled by eUSCI)

PM_UCA3TXD eUSCI_A3 UART TXD (direction controlled by eUSCI – Output)

PM_ UCA3SIMO eUSCI_A3 SPI slave in master out (direction controlled by eUSCI)

15 PM_UCA3CLK eUSCI_A3 clock input/output (direction controlled by eUSCI)

16 PM_UCA3STE eUSCI_A3 SPI slave transmit enable (direction controlled by eUSCI)

PM_UCB0SIMO eUSCI_B0 SPI slave in master out (direction controlled by eUSCI)

PM_UCB0SDA eUSCI_B0 I2C data (open drain and direction controlled by eUSCI)

PM_UCB0SOMI eUSCI_B0 SPI slave out master in (direction controlled by eUSCI)

PM_UCB0SCL eUSCI_B0 I2C clock (open drain and direction controlled by eUSCI)

19 PM_UCB0CLK eUSCI_B0 clock input/output (direction controlled by eUSCI)

20 PM_UCB0STE eUSCI_B0 SPI slave transmit enable (direction controlled by eUSCI)

PM_UCB1SIMO eUSCI_B1 SPI slave in master out (direction controlled by eUSCI)

PM_UCB1SDA eUSCI_B1 I2C data (open drain and direction controlled by eUSCI)

PM_UCB1SOMI eUSCI_B1 SPI slave out master in (direction controlled by eUSCI)

PM_UCB1SCL eUSCI_B1 I2C clock (open drain and direction controlled by eUSCI)

23 PM_UCB1CLK eUSCI_B1 clock input/output (direction controlled by eUSCI)

24 PM_UCB1STE eUSCI_B1 SPI slave transmit enable (direction controlled by eUSCI)

25 PM_TA0.0 TA0 CCR0 capture input CCI0A TA0 CCR0 compare output Out0

26 PM_TA0.1 TA0 CCR1 capture input CCI1A TA0 CCR1 compare output Out1

27 PM_TA0.2 TA0 CCR2 capture input CCI2A TA0 CCR2 compare output Out2

28 PM_TA1.0 TA1 CCR0 capture input CCI0A TA1 CCR0 compare output Out0

29 PM_TA2.0 TA2 CCR0 capture input CCI0A TA2 CCR0 compare output Out0

30 PM_TA3.0 TA3 CCR0 capture input CCI0A TA3 CCR0 compare output Out0

Disables the output driver and the input Schmitt trigger to prevent parasitic cross

31(0FFh)

(1)

PM_ANALOG

currents when applying analog signals.

(1) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored,

which results in a read value of 31.

Table 16. Default Port Mapping

PIN NAME

PxMAPy

INPUT PIN FUNCTION OUTPUT PIN FUNCTION

MNEMONIC

PEU PZ

P2.0/PM_TA0.0 P2.0/PM_TA0.0/COM4 PM_TA0.0 TA0 CCR0 capture input CCI0A TA0 CCR0 compare output Out0

P2.1/PM_TA0.1 P2.1/PM_TA0.1/COM5 PM_TA0.1 TA0 CCR1 capture input CCI1A TA0 CCR1 compare output Out1

P2.2/PM_TA0.2 P2.2/PM_TA0.2/COM6 PM_TA0.2 TA0 CCR2 capture input CCI2A TA0 CCR2 compare output Out2

P2.3/PM_TA1.0 P2.3/PM_TA1.0/COM7 PM_TA1.0 TA1 CCR0 capture input CCI0A TA1 CCR0 compare output Out0

P2.4/PM_TA2.0 P1.1/PM_TA2.0/R23 PM_TA2.0 TA2 CCR0 capture input CCI0A TA2 CCR0 compare output Out0

P2.5/PM_UCB0SOMI/ P2.0/PM_UCB0SOMI/ PM_UCB0SOMI/ eUSCI_B0 SPI slave out master in (direction controlled by eUSCI),

PM_UCB0SCL PM_UCB0SCL/R13 PM_UCB0SCL eUSCI_B0 I2C clock (open drain and direction controlled by eUSCI)

P2.6/PM_UCB0SIMO/ P2.6/PM_UCB0SIMO/ PM_UCB0SIMO/ eUSCI_B0 SPI slave in master out (direction controlled by eUSCI),

PM_UCB0SDA PM_UCB0SDA/R03 PM_UCB0SDA eUSCI_B0 I2C data (open drain and direction controlled by eUSCI)

P2.7/PM_UCB0CLK P2.7/PM_UCB0CLK/CB2 PM_UCB0CLK eUSCI_B0 clock input/output (direction controlled by eUSCI)

P3.0/PM_UCA0RXD/ P3.0/PM_UCA0RXD/ PM_UCA0RXD/ eUSCI_A0 UART RXD (direction controlled by eUSCI – input),

PM_UCA0SOMI PM_UCA0SOMI PM_UCA0SOMI eUSCI_A0 SPI slave out master in (direction controlled by eUSCI)

P3.1/PM_UCA0TXD/ P3.1/PM_UCA0TXD/ PM_UCA0TXD/ eUSCI_A0 UART TXD (direction controlled by eUSCI – output),

PM_UCA0SIMO PM_UCA0SIMO/S39 PM_UCA0SIMO eUSCI_A0 SPI slave in master out (direction controlled by eUSCI)

P3.2/PM_UCA0CLK P3.2/PM_UCA0CLK/S38 PM_UCA0CLK eUSCI_A0 clock input/output (direction controlled by eUSCI)

P3.3/PM_UCA1CLK P3.3/PM_UCA1CLK/S37 PM_UCA1CLK eUSCI_A1 clock input/output (direction controlled by eUSCI)

P3.4/PM_UCA1RXD/ P3.4/PM_UCA1RXD/ PM_UCA1RXD/ eUSCI_A1 UART RXD (direction controlled by eUSCI – input),

PM_UCA1SOMI/ PM_UCA1SOMI/S36 PM_UCA1SOMI eUSCI_A1 SPI slave out master in (direction controlled by eUSCI)