Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsDev KitsPCB design board

ECCN 5E002 TSPA - Technology / Software Publicly Available

MSP430F677x

MSP430F676x

MSP430F674x

www.ti.com

SLAS768D –SEPTEMBER 2012–REVISED DECEMBER 2013

Polyphase Metering SoCs

FEATURES

• Accuracy < 0.1% Over 2000:1 Dynamic Range

• Multiple Low-Power Modes

for Phase Current

– Standby Mode (LPM3): 2.1 µA at 3 V,

• Meets or Exceeds ANSI C12.20 and IEC 62053 Wake Up in Less Than 5 µs

Standards

– RTC Mode (LPM3.5): 0.34 µA at 3 V

• Support for Multiple Sensors Such as Current

– Shutdown Mode (LPM4.5): 0.18 µA at 3 V

Transformers, Rogowski Coils, or Shunts

• Up to 512KB of Single-Cycle Flash

• Power Measurement for up to Three Phases

• Up to 32KB of RAM With Single-Cycle Access

Plus Neutral

• Up to Seven Independent 24-Bit Sigma-Delta

• Dedicated Pulse Output Pins for Active and

ADCs With Differential Inputs and Variable

Reactive Energy for Calibration

Gain

• Four-Quadrant Measurement per Phase or

• System 10-Bit 200-ksps ADC

Cumulative

– Six Channels Plus Supply and Temperature

• Exact Phase Angle Measurements

Sensor Measurement

• Digital Phase Correction for Current

• Integrated Hardware AES-128 Module for

Transformers

Encryption

• Temperature Compensated Energy

• Six Enhanced Communications Ports

Measurements

– Configurable Among Four UART, Six SPI,

• 40-Hz to 70-Hz Line Frequency Range Using

and Two I²C Interfaces

Single Calibration

• Four 16-Bit Timers With Nine Total

• Flexible Power Supply Options With Automatic

Capture/Compare Registers

Switching

• 128-Pin LQFP (PEU) Package With 90 I/O Pins

• Display Operates at Very Low Power During

• 100-Pin LQFP (PZ) Package With 62 I/O Pins

AC Mains Failure: 3 µA in LPM3

• Industrial Temperature Range of –40°C to 85°C

• LCD Driver With Contrast Control for up to 320

• 3-Phase Electronic Watt-Hour Meter

Segments

Development Tools

• Password-Protected Real-Time Clock With

– EVM430-F6779 With SLAA577 App Note

Crystal Offset Calibration and Temperature

Compensation – MSP430™ Energy Library

• Integrated Security Modules to Support Anti- • For Complete Module Descriptions, See the

Tamper and Encryption MSP430x5xx and MSP430x6xx Family User's

Guide (SLAU208)

• Multiple Communication Interfaces for Smart

Meter Implementations

APPLICATIONS

• High-Performance 25-MHz CPU With 32-Bit

• 3-Phase Electronic Watt-Hour Meters

Multiplier

• Utility Metering

• Wide Input Supply Voltage Range:

3.6 V Down to 1.8 V

• Energy Monitoring

• Ultra-Low-Power Consumption During Energy

Measurement

– 2.9 mW at 10-MHz Operation (3 V)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2MSP430, Code Composer Studio are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (162 pages)

PAGE 1
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Polyphase Metering SoCs FEATURES 1 • 2 • • • • • • • • • • • • • • • • • • Accuracy < 0.1% Over 2000:1 Dynamic Range for Phase Current Meets or Exceeds ANSI C12.
PAGE 2
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com DESCRIPTION The Texas Instruments MSP430F677x family of polyphase metering SoCs are powerful highly integrated solutions for revenue meters that offer accuracy and low system cost with few external components.
PAGE 3
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 TOTAL Load kWh Sx, COMx Phase C VCC MSP430F677x Phase A R33 RST Phase B LCDCAP VSS Px.x Neutral + IA CT STATUS LEDs ΣΔ Modulator – + IB CT Px.
PAGE 4
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Family members available are summarized in Table 1. Table 1.
PAGE 5
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Functional Block Diagram – MSP430F677xIPEU, MSP430F676xIPEU, and MSP430F674xIPEU XIN XOUT DVCC DVSS AVCC AVSS AUX1 AUX2 AUX3 PA P1.x P2.x RST/NMI PB P3.x P4.x PC P5.x P6.x P7.x PD P8.x PE P9.x P10.x PF P11.
PAGE 6
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com SD0N0 SD0P0 SD1P0 SD1N0 SD2N0 SD2P0 SD3P0 SD3N0 VASYS2 AVSS2 VREF SD4P0 SD4N0 SD5P0 SD5N0 SD6P0 SD6N0 AVSS1 AVCC VASYS1 AUXVCC2 AUXVCC1 VDSYS1 DVSS1 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 1 102 RST/NMI/SBWTDIO XOUT 2 101 PJ.
PAGE 7
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 2. Pinout Differences for MSP430F677xIPEU , MSP430F676xIPEU , and MSP430F674xIPEU PIN NAME PIN NUMBER MSP430F677xIPEU MSP430F676xIPEU MSP430F674xIPEU 46 P6.1/SD4DIO/S39 P6.1/SD4DIO/S39 P6.1/S39 47 P6.2/SD5DIO/S38 P6.2/SD5DIO/S38 P6.2/S38 48 P6.3/SD6DIO/S37 P6.3/S37 P6.
PAGE 8
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com DVSS2 P6.0/S16 P6.1/S15 P6.3/S13 P6.2/S14 P6.4/S12 P6.5/S11 P6.6/S10 P6.7/S9 P7.0/S8 P7.1/S7 P7.2/S6 P7.3/S5 P7.4/S4 P7.5/S3 P7.6/S2 P7.7/S1 P8.0/S0 P8.1/TACLK/RTCCLKCB3 TEST/SBWTCK PJ.0/TDO PJ.1TDI/TCLK PJ.3/TCK SD0P0 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 VDSYS2 SD0N0 2 74 P5.
PAGE 9
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 3. Pinout Differences for MSP430F677xIPZ , MSP430F676xIPZ , and MSP430F674xIPZ PIN NUMBER PIN NAME MSP430F677xIPZ MSP430F676xIPZ MSP430F674xIPZ 11 VREF VREF VREF 12 SD4P0 SD4P0 NC 13 SD4N0 SD4N0 NC 14 SD5P0 SD5P0 NC 15 SD5N0 SD5NO NC 16 SD6P0 NC NC 17 SD6N0 NC NC 72 P5.5/SD4DIO/S19 P5.5/SD4DIO/S19 P5.
PAGE 10
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Table 4. Terminal Functions – PEU Package TERMINAL NAME NO. I/O (1) DESCRIPTION PEU XIN 1 I/O Input terminal for crystal oscillator XOUT 2 I/O Output terminal for crystal oscillator AUXVCC3 3 RTCCAP1 4 I External time capture pin 1 for RTC_C RTCCAP0 5 I External time capture pin 0 for RTC_C P1.
PAGE 11
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 4. Terminal Functions – PEU Package (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION PEU P3.2/PM_UCA0CLK 18 I/O General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A0 clock input/output P3.
PAGE 12
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Table 4. Terminal Functions – PEU Package (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION PEU P3.6/PM_UCA2RXD/ PM_UCA2SOMI 36 I/O General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A2 UART receive data Default mapping: eUSCI_A2 SPI slave out master in P3.
PAGE 13
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 4. Terminal Functions – PEU Package (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION PEU P7.0/S32 53 I/O General-purpose digital I/O LCD segment output S32 P7.1/S31 54 I/O General-purpose digital I/O LCD segment output S31 P7.2/S30 55 I/O General-purpose digital I/O LCD segment output S30 P7.
PAGE 14
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Table 4. Terminal Functions – PEU Package (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION PEU P9.3/S13 74 I/O General-purpose digital I/O LCD segment output S13 P9.4/S12 75 I/O General-purpose digital I/O LCD segment output S12 P9.5/S11 76 I/O General-purpose digital I/O LCD segment output S11 P9.
PAGE 15
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 4. Terminal Functions – PEU Package (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION PEU P2.1/PM_TA0.1/BSL_RX 94 I/O General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: Timer TA0 capture CCR1: CCI1A input, compare: Out1 output Bootstrap loader: Data receive P2.2/PM_TA0.
PAGE 16
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Table 4. Terminal Functions – PEU Package (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION PEU AVCC 121 Analog power supply VASYS1 122 Analog power supply selected between AVCC, AUXVCC1, AUXVCC2.
PAGE 17
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 5. Terminal Functions – PZ Package TERMINAL NAME NO.
PAGE 18
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Table 5. Terminal Functions – PZ Package (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION PZ P1.3/ADC10CLK/A3 34 I/O General-purpose digital I/O with port interrupt ADC10_A clock output Analog input A3 - 10-bit ADC P1.
PAGE 19
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 5. Terminal Functions – PZ Package (continued) TERMINAL NAME P2.5/PM_UCB0SOMI/ PM_UCB0SCL/LCDREF/ R13 NO.
PAGE 20
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Table 5. Terminal Functions – PZ Package (continued) TERMINAL NAME P4.1/PM_UCA3RXD/ PM_UCA3SOMI/S31 NO. I/O (1) DESCRIPTION PZ 60 I/O General-purpose digital I/O with mappable secondary function Default mapping: eUSCI_A3 UART receive data Default mapping: eUSCI_A3 SPI slave out, master in LCD segment output S31 P4.
PAGE 21
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 5. Terminal Functions – PZ Package (continued) TERMINAL NAME P5.6/PM_SD5DIO/S18 NO.
PAGE 22
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Table 5. Terminal Functions – PZ Package (continued) TERMINAL NAME P8.0/S0 NO. I/O (1) DESCRIPTION PZ 93 I/O General-purpose digital I/O LCD segment output S0 General-purpose digital I/O Timer clock input TACLK for TA0, TA1, TA2, TA3 RTCCLK clock output Comparator_B input CB3 P8.1/TACLK/RTCCLK/CB3 94 I/O TEST/SBWTCK 95 I PJ.
PAGE 23
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Development Tools Support All MSP430™ microcontrollers are supported by a wide variety of software and hardware development tools. Tools are available from TI and various third parties. See them all at www.ti.com/msp430tools. Hardware Features See the Code Composer Studio for MSP430 User's Guide (SLAU157) for details on the available features.
PAGE 24
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com SYS/BIOS SYS/BIOS is an advanced real-time operating system for the MSP430 microcontrollers. It features preemptive deterministic multi-tasking, hardware abstraction, memory management, and real-time analysis. SYS/BIOS is available free of charge and is provided with full source code.
PAGE 25
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.
PAGE 26
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Short-Form Description CPU (Link to User's Guide) The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
PAGE 27
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Operating Modes The MSP430 has one active mode and six software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the lowpower mode on return from the interrupt program.
PAGE 28
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Interrupt Vector Addresses The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 8.
PAGE 29
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 8.
PAGE 30
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Memory Organization Table 11.
PAGE 31
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.
PAGE 32
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Bootstrap Loader (BSL) The BSL enables users to program the flash memory or RAM using various serial interfaces. Access to the device memory via the BSL is protected by an user-defined password. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins.
PAGE 33
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Flash Memory (Link to User's Guide) The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory.
PAGE 34
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Auxiliary Supply System (Link to User's Guide) The auxiliary supply system provides the option to operate the device from auxiliary supplies when the primary supply fails. There are two auxiliary supplies (AUXVCC1 and AUXVCC2) supported in MSP430F67xx.
PAGE 35
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 15.
PAGE 36
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Table 16. Default Port Mapping (continued) PIN NAME PEU PxMAPy MNEMONIC PZ INPUT PIN FUNCTION OUTPUT PIN FUNCTION P3.5/PM_UCA1TXD/ PM_UCA1SIMO P3.5/PM_UCA1TXD/ PM_UCA1SIMO/S35 PM_UCA1TXD/ PM_UCA1SIMO eUSCI_A1 UART TXD (direction controlled by eUSCI – output), eUSCI_A1 SPI slave in master out (direction controlled by eUSCI) P3.
PAGE 37
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 17.
PAGE 38
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Table 18.
PAGE 39
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 TA0 (Link to User's Guide) TA0 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA0 can support multiple capture/compares, PWM outputs, and interval timing. TA0 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
PAGE 40
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com TA2 (Link to User's Guide) TA2 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers. TA2 can support multiple capture/compares, PWM outputs, and interval timing. TA2 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
PAGE 41
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 SD24_B Triggers Table 23 shows the input trigger connections to SD24_B converters from Timer_A modules and output trigger pulse connection from SD24_B to ADC10_A. Table 23. SD24_B Input/Output Trigger Connections DEVICE INPUT SIGNAL MODULE INPUT SIGNAL TA0.1 (internal) SD24_B SD24CHx.SD24SCSx = 001b TA2.1 (internal) SD24_B SD24CHx.
PAGE 42
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Embedded Emulation Module (EEM) (Link to User's Guide) The Embedded Emulation Module (EEM) supports real-time in-system debugging.
PAGE 43
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Peripheral File Map Table 25.
PAGE 44
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Table 26. Special Function Registers (Base Address: 0100h) REGISTER DESCRIPTION REGISTER OFFSET SFR interrupt enable SFRIE1 00h SFR interrupt flag SFRIFG1 02h SFR reset pin control SFRRPCR 04h Table 27.
PAGE 45
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 33.
PAGE 46
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Table 38. Port Mapping for Port P4 (Base Address: 01E0h) REGISTER DESCRIPTION REGISTER OFFSET Port P4.0 mapping register P4MAP0 00h Port P4.1 mapping register P4MAP1 01h Port P4.2 mapping register P4MAP2 02h Port P4.3 mapping register P4MAP3 03h Port P4.4 mapping register P4MAP4 04h Port P4.5 mapping register P4MAP5 05h Port P4.
PAGE 47
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 40.
PAGE 48
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Table 43.
PAGE 49
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 47.
PAGE 50
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Table 51.
PAGE 51
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 52.
PAGE 52
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Table 55.
PAGE 53
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 58.
PAGE 54
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Table 60.
PAGE 55
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 62.
PAGE 56
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Table 64.
PAGE 57
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 64. SD24_B Registers (Base Address: 0800h) (continued) REGISTER DESCRIPTION REGISTER OFFSET SD24_B Converter 5 Conversion Memory High Word register SD24BMEMH5 66h SD24_B Converter 6 Conversion Memory Low Word register SD24BMEML6 68h SD24_B Converter 6 Conversion Memory High Word register SD24BMEMH6 6Ah Table 65.
PAGE 58
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Table 68.
PAGE 59
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) Voltage applied at DVCC to DVSS Voltage applied to any pin (excluding VCORE) –0.3 V to 4.1 V (2) –0.3 V to VCC + 0.
PAGE 60
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Recommended Operating Conditions (continued) Typical values are specified at VCC = 3.
PAGE 61
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.
PAGE 62
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) Temperature (TA) PARAMETER VCC PMMCOREVx -40°C TYP ILPM3 LCD, ext. bias ILPM3 LCD, int.
PAGE 63
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.
PAGE 64
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Outputs – General Purpose I/O (Full Drive Strength) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS I(OHmax) = –3 mA VOH High-level output voltage VCC (1) 1.
PAGE 65
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.
PAGE 66
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Typical Characteristics – Outputs, Full Drive Strength (PxDS.
PAGE 67
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Crystal Oscillator, XT1, Low-Frequency Mode (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER ΔIDVCC.
PAGE 68
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Internal Very-Low-Power Low-Frequency Oscillator (VLO) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC fVLO VLO frequency Measured at ACLK 1.8 V to 3.6 V dfVLO/dT VLO frequency temperature drift Measured at ACLK 1.8 V to 3.6 V Measured at ACLK 1.8 V to 3.
PAGE 69
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 DCO Frequency (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER dfDCO/dVCORE TEST CONDITIONS DCO frequency voltage drift MIN fDCO = 1 MHz TYP MAX 1.9 UNIT %/V Typical DCO Frequency, VCC = 3.0 V, TA = 25°C 100 fDCO – MHz 10 DCOx = 31 1 0.
PAGE 70
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com PMM, SVS High Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN SVSHE = 0, DVCC = 3.
PAGE 71
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 PMM, SVM High Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN SVMHE = 0, DVCC = 3.
PAGE 72
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.
PAGE 73
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Auxiliary Supplies Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VCC NOM MAX Supply voltage range for all supplies at pins DVCC, AVCC, AUX1, AUX2, AUX3 1.8 3.6 PMMCOREVx = 0 1.8 3.6 PMMCOREVx = 1 2.0 3.6 PMMCOREVx = 2 2.2 3.6 PMMCOREVx = 3 2.4 3.
PAGE 74
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.
PAGE 75
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Timer_A over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC fTA Timer_A input clock frequency Internal: SMCLK or ACLK, External: TACLK, Duty cycle = 50% ± 10% 1.8 V, 3 V tTA,cap Timer_A capture timing All capture inputs.
PAGE 76
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.
PAGE 77
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 UCMODEx = 01 tSTE,LEAD STE tSTE,LAG UCMODEx = 10 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tLOW/HIGH tSU,MI tHD,MI SOMI tSTE,ACC tSTE,DIS tVALID,MO SIMO Figure 14.
PAGE 78
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com UCMODEx = 01 tSTE,LEAD STE tSTE,LAG UCMODEx = 10 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tSU,SIMO tLOW/HIGH tHD,SIMO SIMO tACC tDIS tVALID,SOMI SOMI Figure 15.
PAGE 79
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.
PAGE 80
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Inputs – RTC Tamper Detect Pin (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) t(int) (1) (2) PARAMETER TEST CONDITIONS AUXVCC3 MIN External interrupt timing (2) Port P1, P2: P1.x to P2.x, External trigger pulse duration to set interrupt flag 2.
PAGE 81
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 LCD_C Recommended Operating Conditions PARAMETER CONDITIONS MIN NOM MAX UNIT VCC,LCD_C,CP en,3.6 Supply voltage range, LCDCPEN = 1, 0000 < VLCDx ≤ 1111 (charge charge pump enabled, pump enabled, VLCD ≤ 3.6 V) VLCD ≤ 3.6 V 2.2 3.6 V VCC,LCD_C,CP en,3.
PAGE 82
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com LCD_C Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER VLCD LCD voltage TEST CONDITIONS VCC MIN TYP MAX UNIT VLCDx = 0000, VLCDEXT = 0 2.4 V to 3.6 V VCC V LCDCPEN = 1, VLCDx = 0001 2 V to 3.6 V 2.60 V LCDCPEN = 1, VLCDx = 0010 2 V to 3.6 V 2.
PAGE 83
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 SD24_B Power Supply and Recommended Operating Conditions MIN AVCC Analog supply voltage TA Ambient temperature fSD Modulator clock frequency VI VIC VID,FS AVCC = DVCC, AVSS = DVSS = 0 V (1) (2) V 85 °C 0.03 2.
PAGE 84
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com 1600 Input Leakage Current – nA 1400 1200 1000 800 600 400 200 0 -200 -1 -0.5 0 0.5 1 1.5 2 2.5 3 Input Voltage – V Figure 18.
PAGE 85
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.
PAGE 86
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.
PAGE 87
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.
PAGE 88
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com 110.0 theoretical limit (2nd order) 100.0 SINAD − dB 90.0 80.0 70.0 60.0 50.0 10 100 1000 OSR Figure 19. SINAD vs OSR (fSD24 = 1MHz, SD24REFON = 1, SD24GAIN: 1) 100.0 SINAD − dB 80.0 60.0 40.0 20.0 0.0 0 0.2 0.4 0.6 Vpp/Vref/Gain 0.8 1 Figure 20.
PAGE 89
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.
PAGE 90
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com 10-Bit ADC Linearity Parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS EI Integral linearity error 1.4 V ≤ (VeREF+ – VREF–/VeREF–)min ≤ 1.
PAGE 91
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 REF Built-In Reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VREF+ Positive built-in reference voltage TEST CONDITIONS VCC MIN TYP MAX REFVSEL = {2} for 2.5 V, REFON = 1 3V 2.47 2.51 2.55 REFVSEL = {1} for 2 V, REFON = 1 3V 1.96 1.99 2.02 2.2 V, 3 V 1.48 1.
PAGE 92
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Comparator_B over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC TEST CONDITIONS VCC Supply voltage MIN TYP MAX 1.8 3.6 1.
PAGE 93
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.
PAGE 94
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com INPUT/OUTPUT SCHEMATICS Port P1, P1.0 Through P1.3 Input/Output With Schmitt Trigger (MSP430F677xIPEU Only) A0..A3 From ADC P1REN.x P1DIR.x DVSS 0 DVCC 1 00 01 10 11 P1OUT.x 00 From Timer_A, ACLK, ADC10CLK 01 DVSS 11 10 (MSP430F677xIPEU only) P1.0/TA1.1/VeREF-/A0 P1.1/TA2.1/VeREF+/A1 P1.2/ACLK/A2 P1.3/ADC10CLK/A3 P1DS.x P1SEL0.
PAGE 95
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 69. Port P1 (P1.0 Through P1.3) Pin Functions (MSP430F677xIPEU Only) PIN NAME (P1.x) x FUNCTION P1.0 (I/O) P1.0/TA1.1/VeREF-/A0 0 1 2 (1) 3 P1SEL0.x 0 0 0 0 1 TA1.1 1 0 1 N/A 0 1 0 DVSS 1 1 0 VeREF-/A0 X 1 1 I:0; O:1 0 0 TA2.CCI1A 0 0 1 TA2.
PAGE 96
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Port P1, P1.0 Through P1.3 Input/Output With Schmitt Trigger (MSP430F677xIPZ Only) A0..A3 From ADC P1REN.x P1DIR.x DVSS 0 DVCC 1 00 01 10 11 P1OUT.x 00 From Comparator_B From Timer_A, ACLK, ADC10CLK DVSS 01 10 11 (MSP430F677xIPZ only) P1.0/TA1.1/VeREF-/A0 P1.1/TA2.1/CBOUT/VeREF+/A1 P1.2/ACLK/A2 P1.3/ADC10CLK/A3 P1DS.x P1SEL0.x P1SEL1.
PAGE 97
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 70. Port P1 (P1.0, P1.1, P1.2, and P1.3) Pin Functions (MSP430F677xIPZ Only) PIN NAME (P1.x) x FUNCTION P1.0 (I/O) P1.0/TA1.1/VeREF-/A0 0 1 2 (1) 3 P1SEL0.x 0 0 0 0 1 TA1.1 1 0 1 N/A 0 1 0 DVSS 1 1 0 VeREF-/A0 X 1 1 I:0; O:1 0 0 TA2.CCI1A 0 0 1 TA2.
PAGE 98
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Port P1, P1.4 and P1.5 Input/Output With Schmitt Trigger (MSP430F677xIPEU and MSP430F677xIPZ) to Comparator_B from Comparator_B CBPD.z A0..A3 From ADC P1REN.x P1DIR.x DVSS 0 DVCC 1 00 01 10 11 P1OUT.x 00 01 From MCLK, SMCLK 10 DVSS 11 P1.4/MCLK/CB1/A4 P1.5/SMCLK/CB0/A5 P1DS.x P1SEL0.x P1SEL1.x P1IN.x EN Not Used D Bus Keeper P1IE.
PAGE 99
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 71. Port P1 (P1.4 and P1.5) Pin Functions (MSP430F677xIPEU and MSP430F677xIPZ) PIN NAME (P1.x) x FUNCTION P1.4 (I/O) P1.4/MCLK/CB1/A4 4 (1) 5 P1DIR.x P1SEL1.x P1SEL0.x CPBD.
PAGE 100
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Port P1, P1.6 and P1.7 Input/Output With Schmitt Trigger (MSP430F677xIPEU and MSP430F677xIPZ) COM2 to COM3 From LCD_C P1REN.x P1DIR.x DVSS 0 DVCC 1 00 01 10 11 P1OUT.x 00 01 DVSS 10 11 P1.6/COM2 P1.7/COM3 P1DS.x P1SEL0.x P1SEL1.x P1IN.x EN Not Used D Bus Keeper P1IE.x P1IRQ.x Q EN P1IFG.x SET P1SEL.
PAGE 101
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Port P2, P2.0 Through P2.7, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only) P2REN.x P2MAP.x = PMAP_ANALOG P2DIR.x 0 from Port Mapping 1 P2OUT.x 0 from Port Mapping 1 DVSS 0 DVCC 1 (MSP430F677xIPEU only) P2.0/PM_TA0.0 P2.1/PM_TA0.1 P2.2/PM_TA0.2 P2.3/PM_TA1.0 P2.4/PM_TA2.0 P2.5/PM_UCB0SOMI/PM_UCB0SCL P2.
PAGE 102
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Table 73. Port P2 (P2.0 Through P2.7) Pin Functions (MSP430F677xIPEU Only) PIN NAME (P2.x) x FUNCTION P2.0 (I/O) P2.0/PM_TA0.
PAGE 103
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Port P2, P2.0 Through P2.3, Input/Output With Schmitt Trigger (MSP430F677xIPZ Only) COM4 to COM7 from LCD_C P2REN.x P2MAP.x = PMAP_ANALOG P2DIR.x 0 from Port Mapping 1 P2OUT.x 0 from Port Mapping 1 DVSS 0 DVCC 1 (MSP430F677xIPZ only) P2.0/PM_TA0.0/COM4 P2.1/PM_TA0.1/COM5 P2.2/PM_TA0.2/COM6 P2.3/PM_TA1.0/COM7 P2DS.x P2SEL0.x P2IN.
PAGE 104
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Table 74. Port P2 (P2.0 Through P2.3) Pin Functions (MSP430F677xIPZ Only) CONTROL BITS OR SIGNALS (1) PIN NAME (P2.x) x FUNCTION P2.0 (I/O) P2.0/PM_TA0.
PAGE 105
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Port P2, P2.4 Through P2.6, Input/Output With Schmitt Trigger (MSP430F677xIPZ Only) P2REN.x P2MAP.x = PMAP_ANALOG P2DIR.x 0 from Port Mapping 1 P2OUT.x 0 from Port Mapping 1 DVSS 0 DVCC 1 (MSP430F677xIPZ only) P2.4/PM_TA2.0 P2.5/PM_UCB0SOMI/PM_UCB0SCL P2.6/PM_UCB0SIMO/PM_UCB0SDA P2DS.x P2SEL0.x P2IN.
PAGE 106
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Port P2, P2.7, Input/Output With Schmitt Trigger (MSP430F677xIPZ Only) Comparator_B CBPD.z P2REN.x P2MAP.x = PMAP_ANALOG P2DIR.x 0 from Port Mapping 1 P2OUT.x 0 from Port Mapping 1 DVSS 0 DVCC 1 (MSP430F677xIPZ only) P2.7/PM_UCB0CLK/CB2 P2DS.x P2SEL0.x P2IN.x EN to Port Mapping D Bus Keeper P2IE.x P2IRQ.x Q EN P2IFG.
PAGE 107
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Port P3, P3.0 Through P3.7, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only) P3REN.x P3MAP.x = PMAP_ANALOG P3DIR.x 0 from Port Mapping 1 P3OUT.x 0 from Port Mapping 1 DVSS 0 DVCC 1 (MSP430F677xIPEU only) P3.0/PM_UCA0RXD/PM_UCA0SOMI P3.1/PM_UCA0TXD/PM_UCA0SIMO P3.2/PM_UCA0CLK P3.3/PM_UCA1CLK P3.4/PM_UCA1RXD/PM_UCA1SOMI P3.
PAGE 108
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Table 77. Ports P3 (P3.0 Through P3.7) Pin Functions (MSP430F677xIPEU Only) PIN NAME (P3.x) x P3.0/PM_UCA0RXD/ PM_UCA0SOMI 0 FUNCTION P3.
PAGE 109
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Port P3, P3.0, Input/Output With Schmitt Trigger (MSP430F677xIPZ Only) P3REN.x P3MAP.x = PMAP_ANALOG P3DIR.x 0 from Port Mapping 1 P3OUT.x 0 from Port Mapping 1 DVSS 0 DVCC 1 (MSP430F677xIPZ only) P3.0/PM_UCA0RXD/PM_UCA0SOMI P3DS.x P3SEL0.x P3IN.x EN to Port Mapping D Bus Keeper Table 78. Ports P3 (P3.
PAGE 110
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Port P3, P3.1 Through P3.7, Input/Output With Schmitt Trigger (MSP430F677xIPZ Only) S39..S33 LCDS39..LCDS33 P3REN.x P3MAP.x = PMAP_ANALOG P3DIR.x 0 from Port Mapping 1 P3OUT.x 0 from Port Mapping 1 DVSS 0 DVCC 1 (MSP430F677xIPZ only) P3.1/PM_UCA0TXD/PM_UCA0SIMO/S39 P3.2/PM_UCA0CLK/S38 P3.3/PM_UCA1CLK/S37 P3.
PAGE 111
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 79. Ports P3 (P3.1 Through P3.7) Pin Functions (MSP430F677xIPZ Only) PIN NAME (P3.x) x FUNCTION P3.1 (I/O) P3.
PAGE 112
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Port P4, P4.0 Through P4.7, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only) P4REN.x P4MAP.x = PMAP_ANALOG P4DIR.x 0 from Port Mapping 1 P4OUT.x 0 from Port Mapping 1 DVSS 0 DVCC 1 (MSP430F677xIPEU only) P4.0/PM_UCA2CLK P4.1/PM_UCA3RXD/PM_UCA3SOMI P4.2/PM_UCA3TXD/PM_UCA3SIMO P4.3/PM_UCA3CLK P4.4/PM_UCB1SOMI/PM_UCB1SCL P4.
PAGE 113
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 80. Port P4 (P4.0 Through P4.7) Pin Functions (MSP430F677xIPEU Only) PIN NAME (P4.x) x FUNCTION P4.0 (I/O) P4.
PAGE 114
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Port P4, P4.0 Through P4.7, Input/Output With Schmitt Trigger (MSP430F677xIPZ Only) S32..S25 LCDS32..LCDS25 P4REN.x P4MAP.x = PMAP_ANALOG P4DIR.x 0 from Port Mapping 1 P4OUT.x 0 from Port Mapping 1 DVSS 0 DVCC 1 (MSP430F677xIPZ only) P4.0/PM_UCA2CLK/S32 P4.1/PM_UCA3RXD/PM_UCA3SOMI/S31 P4.2/PM_UCA3TXD/PM_UCA3SIMO/S30 P4.
PAGE 115
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 81. Port P4 (P4.0 Through P4.7) Pin Functions (MSP430F677xIPZ Only) PIN NAME (P4.x) x FUNCTION P4.0 (I/O) P4.
PAGE 116
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Port P5, P5.0 Through P5.3, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only) COM4 to COM7 From LCD_C P5REN.x P5DIR.x DVSS 0 DVCC 1 00 01 10 11 P5OUT.x 00 01 DVSS 10 11 (MSP430F677xIPEU only) P5.0/COM4 P5.1/COM5 P5.2/COM6 P5.3/COM7 P5DS.x P5SEL0.x P5SEL1.x P5IN.
PAGE 117
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 82. Port P5 (P5.0 Through P5.3) Pin Functions (MSP430F677xIPEU Only) PIN NAME (P5.x) x FUNCTION P5.0 (I/O) P5.
PAGE 118
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Port P5, P5.4 Through P5.6, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only) R23, R13, R03, LCDREF P5REN.x P5DIR.x DVSS 0 DVCC 1 00 01 from SD24_B 10 11 P5OUT.x 00 01 from SD24_B 10 DVSS 11 (MSP430F677xIPEU only) P5.4/SDCLK/R23 P5.5/SD0DIO/LCDREF/R13 P5.6/SD1DIO/R03 P5DS.x P5SEL0.x P5SEL1.x P5IN.
PAGE 119
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 83. Port P5 (P5.4 Through P5.6) Pin Functions (MSP430F677xIPEU Only) PIN NAME (P5.x) x FUNCTION P5.4 (I/O) P5.4/SDCLK/R23 4 (1) 6 P5SEL0.x 0 0 X 0 1 N/A 0 1 0 DVSS 1 1 0 X 1 1 I:0; O:1 0 0 Secondary digital function X 0 1 N/A 0 1 0 DVSS 1 1 0 LCDREF/R13 X 1 1 P5.6 (I/O) PT.6/SD1DIO/R03 P5SEL1.
PAGE 120
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Port P5, P5.7, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only) to Comparator_B CBPD.z P5REN.x P5DIR.x DVSS 0 DVCC 1 00 01 from SD24_B 10 11 P5OUT.x 00 01 10 from SD24_B 11 (MSP430F677xIPEU only) P5.7/SD2DIO/CB2 P5DS.x P5SEL0.x P5SEL1.x P5IN.x EN to SD24_B D Bus Keeper Table 84. Port P5 (P5.
PAGE 121
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Port P5, P5.0 Through P5.7, Input/Output With Schmitt Trigger (MSP430F677xIPZ Only) S24..S17 LCDS24..LCDS17 P5REN.x P5DIR.x DVSS 0 DVCC 1 00 01 from SD24_B 10 11 P5OUT.x 00 01 from SD24_B 10 11 (MSP430F677xIPZ only) P5.0/SDCLK/S24 P5.1/SD0DIO/S23 P5.2/SD1DIO/S22 P5.3/SD2DIO/S21 P5.4/SD3DIO/S20 P5.5/SD4DIO/S19 P5.6/SD5DIO/S18 P5.
PAGE 122
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Table 85. Port P5 (P5.0 Through P5.7) Pin Function (MSP430F677xIPZ Only) PIN NAME (P5.x) x FUNCTION P5.0 (I/O) P5.0/SDCLK/S24 0 Secondary digital function S24 P5.1 (I/O) P5.1/SD0DIO/S23 1 Secondary digital function S23 P5.2 (I/O) P5.2/SD1DIO/S22 2 Secondary digital function S22 P5.3 (I/O) P5.
PAGE 123
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Port P6, P6.0, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only) P6REN.x P6DIR.x 0 from SD24_B 1 P6OUT.x 0 from SD24_B 1 DVSS 0 DVCC 1 (MSP430F677xIPEU only) P6.0/SD3DIO P6DS.x P6SEL0.x P6IN.x EN to SD24_B D Bus Keeper Table 86. Port P6 (P6.0) Pin Functions (MSP430F677xIPEU Only) PIN NAME (P6.x) P6.
PAGE 124
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Port P6, P6.1 Through P6.3, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only) S39...S37 LCDS39...LCDS37 P6REN.x P6DIR.x 0 from SD24_B 1 P6OUT.x 0 from SD24_B 1 DVSS 0 DVCC 1 (MSP430F677xIPEU only) P6.1/SD4DIO/S39 P6.2/SD5DIO/S38 P6.3/SD6DIO/S37 P6DS.x P6SEL0.x P6IN.
PAGE 125
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 87. Port P6 (P6.1 Through P6.3) Pin Functions (MSP430F677xIPEU Only) PIN NAME (P6.x) x FUNCTION P6.1 (I/O) P6.1/SD4DIO/S39 1 2 (1) 3 P6SEL0.x LCD39..37 I:0; O:1 0 0 X 1 0 S39 X X 1 I:0; O:1 0 0 Secondary digital function X 1 0 S38 X X 1 I:0; O:1 0 0 P6.3 (I/O) P6.3/SD6DIO/S37 P6DIR.
PAGE 126
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Port P6, P6.4 Through P6.7, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only) S36...S0 LCDS36...LCDS0 P6REN.x P6DIR.x DVSS 0 DVCC 1 0 1 P6OUT.x 0 DVSS 1 (MSP430F677xIPEU only) P6.4/S36 P6.5/S35 P6.6/S34 P6.7/S33 P6DS.x P6SEL0.x P6IN.
PAGE 127
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 88. Port P6 (P6.4 Through P6.7) Pin Functions (MSP430F67xxIPEU Only) PIN NAME (P6.x) x FUNCTION P6.4 (I/O) P6.4/S36 4 5 0 0 1 0 DVSS 1 1 0 S36 X X 1 I:0; O:1 0 0 N/A 0 1 0 DVSS 1 1 0 N/A (1) 7 X X 1 I:0; O:1 0 0 0 1 0 DVSS 1 1 0 S34 X X 1 I:0; O:1 0 0 0 1 0 P6.7 (I/O) P6.7/S33 LCD36..
PAGE 128
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Port P6, P6.0 Through P6.7, Input/Output With Schmitt Trigger (MSP430F677xIPZ Only) S16...S9 LCDS16...LCDS9 P6REN.x P6DIR.x DVSS 0 DVCC 1 0 1 P6OUT.x 0 DVSS 1 (MSP430F677xIPZ only) P6.0/S16 P6.1/S15 P6.2/S14 P6.3/S13 P6.4/S12 P6.5/S11 P6.6/S10 P6.7/S9 P6DS.x P6SEL0.x P6IN.
PAGE 129
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 89. Port P6 (P6.0 Through P6.7) Pin Functions (MSP430F67xxIPZ Only) PIN NAME (P6.x) x FUNCTION P6.0 (I/O) P6.
PAGE 130
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Port P7, P7.0 Through P7.7, Input/Output With Schmitt Trigger (MSP430F67xxIPEU Only) S32...S25 LCDS32...LCDS25 P7REN.x P7DIR.x DVSS 0 DVCC 1 0 1 P7OUT.x 0 DVSS 1 (MSP430F677xIPEU only) P7.0/S32 P7.1/S31 P7.2/S30 P7.3/S29 P7.4/S28 P7.5/S27 P7.6/S26 P7.7/S25 P7DS.x P7SEL0.x P7IN.
PAGE 131
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 90. Port P7 (P7.0 Through P7.7) Pin Functions (MSP430F67xxIPEU Only) PIN NAME (P7.x) x FUNCTION P7.0 (I/O) P7.
PAGE 132
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Port P7, P7.0 Through P7.7, Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only) S8...S1 LCDS8...LCDS1 P7REN.x P7DIR.x DVSS 0 DVCC 1 0 1 P7OUT.x 0 DVSS 1 (MSP430F677xIPZ only) P7.0/S8 P7.1/S7 P7.2/S6 P7.3/S5 P7.4/S4 P7.5/S3 P7.6/S2 P7.7/S1 P7DS.x P7SEL0.x P7IN.
PAGE 133
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 91. Port P7 (P7.0 Through P7.7) Pin Functions (MSP430F67xxIPZ Only) PIN NAME (P7.x) x FUNCTION P7.0 (I/O) P7.
PAGE 134
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Port P8, P8.0 Through P8.7, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only) S24...S17 LCDS24...LCDS17 P8REN.x P8DIR.x DVSS 0 DVCC 1 0 1 P8OUT.x 0 DVSS 1 (MSP430F677xIPEU only) P8.0/S24 P8.1/S23 P8.2/S22 P8.3/S21 P8.4/S20 P8.5/S19 P8.6/S18 P8.7/S17 P8DS.x P8SEL0.x P8IN.
PAGE 135
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 92. Port P8 (P8.0 Through P8.7) Pin Functions (MSP430F677xIPEU Only) PIN NAME (P8.x) x FUNCTION P8.0 (I/O) P8.
PAGE 136
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Port P8, P8.0, Input/Output With Schmitt Trigger (MSP430F677xIPZ Only) S0 LCDS0 P8REN.x P8DIR.x DVSS 0 DVCC 1 0 1 P8OUT.x 0 DVSS 1 (MSP430F677xIPZ only) P8.0/S0 P8DS.x P8SEL0.x P8IN.x EN Not Used D Bus Keeper Table 93. Port P8 (P8.0) Pin Functions (MSP430F677xIPZ Only) PIN NAME (P8.x) x FUNCTION P8.0 (I/O) P8.
PAGE 137
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Port P8, P8.1, Input/Output With Schmitt Trigger (MSP430F677xIPZ Only) to Comparator_B CBPD.z P8REN.x DVSS 0 DVCC 1 0 P8DIR.x 1 P8OUT.x 0 RTCCLK 1 (MSP430F677xIPZ only) P8.1/TACLK/RTCCLK/CB3 P8DS.x P8SEL0.x P8IN.x EN to TACLK D Bus Keeper Table 94. Port P8 (P8.1) Pin Functions (MSP430F677xIPZ Only) PIN NAME (P8.x) x FUNCTION P8.
PAGE 138
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Port P9, P9.0 Through P9.7, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only) S16...S9 LCDS16...LCDS9 P9REN.x P9DIR.x DVSS 0 DVCC 1 0 1 P9OUT.x 0 DVSS 1 (MSP430F677xIPEU only) P9.0/S16 P9.1/S15 P9.2/S14 P9.3/S13 P9.4/S12 P9.5/S11 P9.6/S10 P9.7/S9 P9DS.x P9SEL0.x P9IN.
PAGE 139
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 95. Port P9 (P9.0 to P9.7) Pin Functions (MSP430F677xIPEU Only) PIN NAME (P9.x) x FUNCTION P9.0 (I/O) P9.
PAGE 140
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Port P10, P10.0 Through P10.7, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only) S8...S1 LCDS8...LCDS1 P10REN.x P10DIR.x DVSS 0 DVCC 1 0 1 P10OUT.x 0 DVSS 1 (MSP430F677xIPEU only) P10.0/S8 P10.1/S7 P10.2/S6 P10.3/S5 P10.4/S4 P10.5/S3 P10.6/S2 P10.7/S1 P10DS.x P10SEL0.x P10IN.
PAGE 141
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 96. Port P10 (P10.0 Through P10.7) Pin Functions (MSP430F677xIPEU Only) PIN NAME (P10.x) x FUNCTION P10.0 (I/O) P10.
PAGE 142
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Port P11, P11.0, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only) S0 LCDS0 P11REN.x P11DIR.x DVSS 0 DVCC 1 0 1 P11OUT.x 0 DVSS 1 (MSP430F677xIPEU only) P11.0/S0 P11DS.x P11SEL0.x P11IN.x EN Not Used D Bus Keeper Table 97. Port P11 (P11.0) Pin Functions (MSP430F677xIPEU Only) PIN NAME (P11.x) x FUNCTION P11.0 (I/O) P11.
PAGE 143
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Port P11, P11.1, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only) to Comparator_B CBPD.z P11REN.x DVSS 0 DVCC 1 0 P11DIR.x 1 P11OUT.x 0 from Timer_A 1 (MSP430F677xIPEU only) P11.1/TA3.1/CB3 P11DS.x P11SEL0.x P11IN.x EN to Timer_A D Bus Keeper Table 98. Port P11 (P11.1) Pin Functions (MSP430F677xIPEU Only) PIN NAME (P11.
PAGE 144
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Port P11, P11.2 and P11.3, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only) P11REN.x DVSS 0 DVCC 1 0 P11DIR.x 1 0 P11OUT.x 1 from Timer_A (MSP430F677xIPEU only) P11.2/TA1.1 P11.3/TA2.1 P11DS.x P11SEL0.x P11IN.x EN to Timer_A D Bus Keeper Table 99. Port P11 (P11.2 and P11.
PAGE 145
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Port P11, P11.4 and P11.5, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only) P11REN.x DVSS 0 DVCC 1 0 P11DIR.x 1 P11OUT.x 0 from Comparator_B RTCCLK 1 (MSP430F677xIPEU only) P11.4/CBOUT P11.5/TACLK/RTCCLK P11DS.x P11SEL0.x P11IN.x EN to TACLK D Bus Keeper Table 100. Port P11 (P11.4 and P11.
PAGE 146
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Port J, J.0, JTAG pin TDO, Input/Output With Schmitt Trigger or Output Pad Logic PJREN.x PJDIR.x 0 DVCC 1 PJOUT.x 00 From JTAG 01 SMCLK 10 DVSS 0 DVCC 1 1 PJ.0/SMCLK/TDO PJDS.0 0: Low drive 1: High drive 11 PJSEL.x From JTAG PJIN.x Bus Holder EN D Port J, J.1 to J.
PAGE 147
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 101. Port PJ (PJ.0 to PJ.3) Pin Functions CONTROL BITS OR SIGNALS (1) PIN NAME (PJ.x) PJ.0/SMCLK/TDO PJ.1/MCLK/TDI/TCLK x 0 1 FUNCTION PJ.0 (I/O) (2) PJ.3/ACLK/TCK 3 0 0 1 1 0 TDO (3) x x 1 I: 0; O: 1 0 0 1 1 0 x x 1 PJ.1 (I/O) (2) PJ.
PAGE 148
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Device Descriptors (TLV) list the complete contents of the device descriptor tag-length-value (TLV) structure for each device type. Table 102.
PAGE 149
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Table 103.
PAGE 150
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 www.ti.com Table 104.
PAGE 151
ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, MSP430F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 REVISION HISTORY REVISION DESCRIPTION SLAS768 Product Preview release SLAS768A Production Data release SLAS768B Made editorial changes to Features. Recommended Operating Conditions, Added TYP test conditions. Active Mode Supply Current Into VCC Excluding External Current, Updated current values.
PAGE 152
PACKAGE OPTION ADDENDUM www.ti.
PAGE 153
PACKAGE OPTION ADDENDUM www.ti.
PAGE 154
PACKAGE OPTION ADDENDUM www.ti.
PAGE 155
PACKAGE OPTION ADDENDUM www.ti.
PAGE 156
PACKAGE OPTION ADDENDUM www.ti.com 22-Apr-2014 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PAGE 157
PACKAGE MATERIALS INFORMATION www.ti.com 1-Apr-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing MSP430F6745IPEUR LQFP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2.25 24.0 44.0 Q1 PEU 128 750 330.0 44.4 17.0 23.0 MSP430F6745IPZR LQFP PZ 100 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 Q2 MSP430F6746IPEUR LQFP PEU 128 750 330.0 44.4 17.0 23.0 2.25 24.0 44.
PAGE 158
PACKAGE MATERIALS INFORMATION www.ti.com 1-Apr-2014 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant MSP430F6769IPZR LQFP PZ 100 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 Q2 MSP430F6775IPEUR LQFP PEU 128 750 330.0 44.4 17.0 23.0 2.25 24.0 44.0 Q1 MSP430F6775IPZR LQFP PZ 100 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 Q2 MSP430F6776IPEUR LQFP PEU 128 750 330.0 44.4 17.
PAGE 159
PACKAGE MATERIALS INFORMATION www.ti.com 1-Apr-2014 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430F6748IPEUR LQFP PEU 128 750 367.0 367.0 67.0 MSP430F6748IPZR LQFP PZ 100 1000 367.0 367.0 45.0 MSP430F6749IPEUR LQFP PEU 128 750 367.0 367.0 67.0 MSP430F6765IPEUR LQFP PEU 128 750 367.0 367.0 67.0 MSP430F6765IPZR LQFP PZ 100 1000 367.0 367.0 45.0 MSP430F6766IPEUR LQFP PEU 128 750 367.0 367.0 67.
PAGE 160
PAGE 161
MECHANICAL DATA MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996 PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 75 0,08 M 51 76 50 100 26 1 0,13 NOM 25 12,00 TYP Gage Plane 14,20 SQ 13,80 16,20 SQ 15,80 0,05 MIN 1,45 1,35 0,25 0°– 7° 0,75 0,45 Seating Plane 0,08 1,60 MAX 4040149 /B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
PAGE 162
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.