Datasheet
SDA
SCL
t
HD,DAT
t
SU,DAT
t
HD,STA
t
HIGH
t
LOW
t
BUF
t
HD,STA
t
SU,STA
t
SP
t
SU,STO
ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
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SLAS554H –MAY 2009–REVISED SEPTEMBER 2013
USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 19)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
Internal: SMCLK, ACLK
f
USCI
USCI input clock frequency External: UCLK f
SYSTEM
MHz
Duty cycle = 50% ± 10%
f
SCL
SCL clock frequency 2.2 V, 3 V 0 400 kHz
f
SCL
≤ 100 kHz 4.0
t
HD,STA
Hold time (repeated) START 2.2 V, 3 V µs
f
SCL
> 100 kHz 0.6
f
SCL
≤ 100 kHz 4.7
t
SU,STA
Setup time for a repeated START 2.2 V, 3 V µs
f
SCL
> 100 kHz 0.6
t
HD,DAT
Data hold time 2.2 V, 3 V 0 ns
t
SU,DAT
Data setup time 2.2 V, 3 V 250 ns
f
SCL
≤ 100 kHz 4.0
t
SU,STO
Setup time for STOP 2.2 V, 3 V µs
f
SCL
> 100 kHz 0.6
2.2 V 50 600
t
SP
Pulse duration of spikes suppressed by input filter ns
3 V 50 600
Figure 19. I2C Mode Timing
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