Datasheet

RGC PACKAGE
(TOP VIEW)
CC430F613x
P3.7/PM_SMCLK/S17
P2.0/PM_CBOUT1/PM_TA1CLK/CB0/A0
17
64
P3.6/PM_RFGDO1/S16
P2.1/PM_TA1CCR0A/CB1/A1
18
63
P3.5/PM_TA0CCR4A/S15
P2.2/PM_TA1CCR1A/CB2/A2
19
62
P2.3/PM_TA1CCR2A/CB3/A3
P3.4/PM_TA0CCR3A/S14
20
61
P2.4/PM_RTCCLK/CB4/A4/VREF-/VeREF-
P3.3/PM_TA0CCR2A/S13
21
60
P2.5/ /CB5/A5PM_SVMOUT /VREF+/VeREF+
P3.2/PM_TA0CCR1A/S12
22
59
DVCC
P4.4/S6
29
52
RST/NMI/SBWTDIO
P4.3/S5
30
51
TEST/SBWTCK
P4.2/S4
31
50
PJ.3/TCK
P4.1/S3
32
49
P2.6/PM_ACLK/CB6/A6
P3.1/PM_TA0CCR0A/S11
23
58
P2.7/ /CB7/A7PM_ADC12CLK/PM_DMAE0
P3.0/PM_CBOUT0/PM_TA0CLK/S10
24
57
AVCC
DVCC
25
56
P5.0/XIN
P4.7/S9
26
55
P5.1/XOUT
P4.6/S8
27
54
AVSS
P4.5/S7
28
53
P4.0/S2P1.0/PM_RFGDO0/S18
3316
P5.3/S1
P1.1/PM_RFGDO2/S19
3415
P5.2/S0
P1.2/PM_UCB0SOMI/PM_UCB0SCL/S20
35
14
RF_XINP1.3/PM_UCB0SIMO/PM_UCB0SDA/S21
3613
RF_XOUTP1.4/PM_UCB0CLK/PM_UCA0STE/S22
37
12
AVCC_RFDVCC
38
11
GUARD
LCDCAP/R33
45
4
PJ.0/TDO
P1.5/PM_UCA0RXD/PM_UCA0SOMI/R23
463
PJ.1/TDI/TCLK
P1.6/PM_UCA0TXD/PM_UCA0SIMO/R13/LCDREF
472
PJ.2/TMS
P1.7/PM_UCA0CLK/PM_UCB0STE/R03
48
1
AVCC_RF VCORE
3910
RF_P
P5.4/S23
409
RF_NP5.5/COM3/S24
41
8
AVCC_RFP5.6/COM2/S25
42
7
AVCC_RF
P5.7/COM1/S26
436
R_BIAS
COM0
44
5
VSS
Exposed die
attached pad
ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
www.ti.com SLAS554H –MAY 2009–REVISED SEPTEMBER 2013
NOTE: The secondary digital functions on ports P1, P2, and P3 are fully mappable. This pinout shows only the default
mapping. See Table 9 for details.
CAUTION: The LCDCAP/R33 must be connected to VSS if not used.
Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137
CC430F5135 CC430F5133