Datasheet
ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
www.ti.com
SLAS554H –MAY 2009–REVISED SEPTEMBER 2013
Port Mapping Controller
The port mapping controller allows the flexible and re-configurable mapping of digital functions to port pins of
ports P1 through P3.
Table 9. Port Mapping, Mnemonics and Functions
OUTPUT PIN FUNCTION
VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION (PxDIR.y = 0)
(PxDIR.y = 1)
0 PM_NONE None DVSS
Comparator_B output (on TA0 clock
PM_CBOUT0
input)
1
(1)
PM_TA0CLK TA0 clock input -
Comparator_B output (on TA1 clock
PM_CBOUT1 -
input)
2
(1)
PM_TA1CLK TA1 clock input -
3 PM_ACLK None ACLK output
4 PM_MCLK None MCLK output
5 PM_SMCLK None SMCLK output
6 PM_RTCCLK None RTCCLK output
PM_ADC12CLK - ADC12CLK output
7
(1)
PM_DMAE0 DMA external trigger input -
8 PM_SVMOUT None SVM output
9 PM_TA0CCR0A TA0 CCR0 capture input CCI0A TA0 CCR0 compare output Out0
10 PM_TA0CCR1A TA0 CCR1 capture input CCI1A TA0 CCR1 compare output Out1
11 PM_TA0CCR2A TA0 CCR2 capture input CCI2A TA0 CCR2 compare output Out2
12 PM_TA0CCR3A TA0 CCR3 capture input CCI3A TA0 CCR3 compare output Out3
13 PM_TA0CCR4A TA0 CCR4 capture input CCI4A TA0 CCR4 compare output Out4
14 PM_TA1CCR0A TA1 CCR0 capture input CCI0A TA1 CCR0 compare output Out0
15 PM_TA1CCR1A TA1 CCR1 capture input CCI1A TA1 CCR1 compare output Out1
16 PM_TA1CCR2A TA1 CCR2 capture input CCI2A TA1 CCR2 compare output Out2
PM_UCA0RXD USCI_A0 UART RXD (Direction controlled by USCI - input)
17
(2)
PM_UCA0SOMI USCI_A0 SPI slave out master in (direction controlled by USCI)
PM_UCA0TXD USCI_A0 UART TXD (Direction controlled by USCI - output)
18
(2)
PM_UCA0SIMO USCI_A0 SPI slave in master out (direction controlled by USCI)
PM_UCA0CLK USCI_A0 clock input/output (direction controlled by USCI)
19
(3)
PM_UCB0STE USCI_B0 SPI slave transmit enable (direction controlled by USCI - input)
PM_UCB0SOMI USCI_B0 SPI slave out master in (direction controlled by USCI)
20
(4)
PM_UCB0SCL USCI_B0 I2C clock (open drain and direction controlled by USCI)
PM_UCB0SIMO USCI_B0 SPI slave in master out (direction controlled by USCI)
21
(4)
PM_UCB0SDA USCI_B0 I2C data (open drain and direction controlled by USCI)
PM_UCB0CLK USCI_B0 clock input/output (direction controlled by USCI)
22
(5)
PM_UCA0STE USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)
23 PM_RFGDO0 Radio GDO0 (direction controlled by Radio)
24 PM_RFGDO1 Radio GDO1 (direction controlled by Radio)
25 PM_RFGDO2 Radio GDO2 (direction controlled by Radio)
26 Reserved None DVSS
(1) Input or output function is selected by the corresponding setting in the port direction register PxDIR.
(2) UART or SPI functionality is determined by the selected USCI mode.
(3) UCA0CLK function takes precedence over UCB0STE function. If the mapped pin is required as UCA0CLK input or output USCI_B0 will
be forced to 3-wire SPI mode even if 4-wire mode is selected.
(4) SPI or I2C functionality is determined by the selected USCI mode. In case the I2C functionality is selected the output of the mapped pin
drives only the logical 0 to V
SS
level.
(5) UCB0CLK function takes precedence over UCA0STE function. If the mapped pin is required as UCB0CLK input or output USCI_A0 will
be forced to 3-wire SPI mode even if 4-wire mode is selected.
Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137
CC430F5135 CC430F5133