Datasheet

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MSP432P401R, MSP432P401M
SLAS826 –MARCH 2015 www.ti.com
CAUTION
The WDT should ideally be configured to generate a Hard Reset into the
system. A Soft Reset will reset the CPU, but leave the rest of the system and
peripherals unaffected. As a result if the WDT is configured to generate a Soft
Reset, the application should assume responsibility for the fact that a Soft
Reset can corrupt an ongoing transaction from the CPU into the system.
6.8.8 ADC14
The ADC14 module supports fast, 14-bit analog-to-digital conversions with differential and single-ended
inputs. The module implements a 14-bit SAR core, sample select control, reference generator and a
conversion result buffer. The window comparators with a lower and upper limit allow CPU independent
result monitoring through different window comparator interrupt flags.
The available ADC14 external trigger sources are summarized in Table 6-27.
The available multiplexing between internal and external analog inputs of ADC14 is listed in Table 6-
28,Table 6-29,Table 6-30.
Table 6-27. ADC14 Trigger Signal Connections
ADC14SHSx
CONNECTED TRIGGER
SOURCE
BINARY DECIMAL
000 0 Software (ADC14SC)
001 1 TA0_C1
010 2 TA0_C2
011 3 TA1_C1
100 4 TA1_C2
101 5 TA2_C1
110 6 TA2_C2
111 7 TA3_C1
Table 6-28. ADC14 Channel Mapping on 100PZ Devices
EXTERNAL INTERNAL CHANNEL
ADC14 CHANNEL CHANNEL SOURCE SOURCE CONTROL BIT
(2)
(CONTROL BIT = 0) (CONTROL BIT = 1)
(1)
Channel 23 A23 Battery Monitor ADC14BATMAP
Channel 22 A22 Temperature Sensor ADC14TCMAP
Channel 21 A21 NA (Reserved) ADC14CH0MAP
Channel 20 A20 NA (Reserved) ADC14CH1MAP
Channel 19 A19 NA (Reserved) ADC14CH2MAP
Channel 18 A18 NA (Reserved) ADC14CH3MAP
(1) If an internal source is marked as NA or Reserved, it indicates that only the external source is
available for that channel.
(2) Refer to theADC14 chapter in the MSP432P4xx Family Technical Reference Manual for details on the
registers that contain the control bits listed in the table.
96 Detailed Description Copyright © 2015, Texas Instruments Incorporated
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