Datasheet

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MSP432P401R, MSP432P401M
SLAS826 –MARCH 2015 www.ti.com
Table 6-20. Default Mapping (continued)
PIN NAME PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
P3.3/PM_UCA2TXD/ PM_UCA2TXD/ eUSCI_A2 UART TXD (direction controlled by eUSCI – output)/
PM_UCA2SIMO PM_UCA2SIMO eUSCI_A2 SPI slave in master out (direction controlled by eUSCI)
P3.4/PM_UCB2STE PM_UCB2STE eUSCI_B2 SPI slave transmit enable (direction controlled by eUSCI)
P3.5/PM_UCB2CLK PM_UCB2CLK eUSCI_B2 clock input/output (direction controlled by eUSCI)
P3.6/PM_UCB2SIMO/ PM_UCB2SIMO/ eUSCI_B2 SPI slave in master out (direction controlled by eUSCI)/
PM_UCB2SDA PM_UCB2SDA eUSCI_B2 I
2
C data (open drain and direction controlled by eUSCI)
P3.7/PM_UCB2SOMI/ PM_UCB2SOMI/ eUSCI_B2 SPI slave out master in (direction controlled by eUSCI)/
PM_UCB2SCL PM_UCB2SCL eUSCI_B2 I
2
C clock (open drain and direction controlled by eUSCI)
P7.0/PM_SMCLK/ PM_SMCLK/
DMAE0 input SMCLK
PM_DMAE0 PM_DMAE0
P7.1/PM_C0OUT/ PM_C0OUT/
Timer_A0 external clock input Comparator-E0 output
PM_TA0CLK PM_TA0CLK
P7.2/PM_C1OUT/ PM_C1OUT/
Timer_A1 external clock input Comparator-E1 output
PM_TA1CLK PM_TA1CLK
P7.3/PM_TA0.0 PM_TA0.0 TA0 CCR0 capture input CCI0A TA0 CCR0 compare output Out0
P7.4/PM_TA1.4/C0.5
(1)
PM_TA1.4 TA1 CCR4 capture input CCI4A TA1 CCR4 compare output Out4
P7.5/PM_TA1.3/C0.4
(1)
PM_TA1.3 TA1 CCR3 capture input CCI3A TA1 CCR3 compare output Out3
P7.6/PM_TA1.2/C0.3
(1)
PM_TA1.2 TA1 CCR2 capture input CCI2A TA1 CCR2 compare output Out2
P7.7/PM_TA1.1/C0.2
(1)
PM_TA1.1 TA1 CCR1 capture input CCI1A TA1 CCR1 compare output Out1
6.8.3 Timer_A
Timers TA0, TA1, TA2 and TA3 are 16-bit timers/counters (Timer_A type) with five capture/compare
registers each. Each timer supports multiple capture/compares, PWM outputs, and interval timing. Each
has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions
and from each of the capture/compare registers.
6.8.3.1 Timer_A Signal Connection Tables
Table 6-21 through Table 6-24 list the interface signals of the Timer_A modules on the device and
connections of the interface signals to the corresponding pins or internal signals. The following rules apply
to the naming conventions used.
• The first column lists the device level pin or internal signal that sources the clocks and/or triggers into
the Timer. The default assumption is that these are pins, unless specifically marked as (internal).
Nomenclature used for internal signals is as follows:
– CxOUT: output from Comparator 'x'.
– TAx_Cy: Output from Timer 'x', Capture/Compare module 'y'.
• The second column lists the input signals of the Timer module.
• The third column lists the submodule of the Timer and also implies the functionality (Timer, Capture
(Inputs or Triggers), or Compare (Outputs or PWM)).
• The fourth column lists the output signals of the Timer module.
• The fifth column lists the device level pin or internal signal that is driven by the outputs of the Timer.
The default assumption is that these are pins, unless specifically marked as (internal).
NOTE
The pin names listed in the tables are the complete names. It is the responsibility of the
software to ensure that the pin is used in the intended mode for the targeted Timer
functionality.
90 Detailed Description Copyright © 2015, Texas Instruments Incorporated
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