Datasheet

PRODUCTPREVIEW
1P1.0/UCA0STE
2P1.1/UCA0CLK
3P1.2/UCA0RXD/UCA0SOMI
4P1.3/UCA0TXD/UCA0SIMO
5P1.4/UCB0STE
6P1.5/UCB0CLK
7P1.6/UCB0SIMO/UCB0SDA
8P1.7/UCB0SOMI/UCB0SCL
9
DVSS1
10
VSW
11
DVCC1
12
VCORE
13P2.0/PM_UCA1STE
14P2.1/PM_UCA1CLK
15P2.2/PM_UCA1RXD/PM_UCA1SOMI
16P2.3/PM_UCA1TXD/PM_UCA1SIMO
17
P8.0/UCB3STE/TA1.0/C0.1
18
P8.1/UCB3CLK/TA2.0/C0.0
19
P3.0/PM_UCA2STE
20
P3.1/PM_UCA2CLK
21
P3.2/PM_UCA2RXD/PM_UCA2SOMI
22
P3.3/PM_UCA2TXD/PM_UCA2SIMO
23
P3.4/PM_UCB2STE
24
P3.5/PM_UCB2CLK
25
P3.6/PM_UCB2SIMO/PM_UCB2SDA
26
P3.7/PM_UCB2SOMI/PM_UCB2SCL
27
AVCC1
28
DCOR
29
AVSS1
30
PJ.0/LFXIN
31
PJ.1/LFXOUT
32
AVSS3
33 P4.2/ACLK/TA2CLK/A11
34 P4.3/MCLK/RTCCLK/A10
35 P4.4/HSMCLK/SVMHOUT/A9
36 P4.5/A8
37 P4.6/A7
38 P4.7/A6
39 P5.0/A5
40 P5.1/A4
41 P5.2/A3
42 P5.3/A2
43 P5.4/A1
44 P5.5/A0
45 P5.6/TA2.1/VREF+/VeREF+/C1.7
46 P5.7/TA2.2/VREF-/VeREF-/C1.6
47 DVSS2
48 DVCC2
49
P6.6/TA2.3/UCB3SIMO/UCB3SDA/C1.1
50
P6.7/TA2.4/UCB3SOMI/UCB3SCL/C1.0
51
DVSS3
52
RSTn/NMI
53
AVSS2
54
PJ.2/HFXOUT
55
PJ.3/HFXIN
56
AVCC2
57
P7.0/PM_SMCLK/PM_DMAE0
58
P7.1/PM_C0OUT/PM_TA0CLK
59
P7.2/PM_C1OUT/PM_TA1CLK
60
P7.3/PM_TA0.0
61
PJ.4/TDI/ADC14CLK
62
PJ.5/TDO/SWO
63
SWDIOTMS
64
SWCLKTCK
MSP432P401R, MSP432P401M
www.ti.com SLAS826 –MARCH 2015
Figure 4-3 shows the pinout of the 64-pin RGC package.
Notes:
1. The secondary digital functions on Ports P2, P3, and P7 are fully mappable. The pin designation shows only the
default mapping. See Table 6-19 for details.
2. Glitch filter is implemented on the following 8 digital I/Os: P1.0, P1.4, P1.5, P3.0, P3.4, P3.5, P6.6, P6.7.
TI recommends connecting the thermal pad on the QFN package to DVSS.
4. UART BSL pins: P1.2 - BSLRXD, P1.3 - BSLTXD
5. SPI BSL pins: P1.4 - BSLSTE, P1.5 - BSLCLK, P1.6 - BSLSIMO, P1.7 - BSLSOMI
6. I
2
C BSL pins: P3.6 - BSLSDA, P3.7 - BSLSCL
Figure 4-3. 64-Pin RGC Package (Top View)
Copyright © 2015, Texas Instruments Incorporated Terminal Configuration and Functions 9
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