Datasheet

PRODUCTPREVIEW
MSP432P401R, MSP432P401M
www.ti.com SLAS826 –MARCH 2015
Table 6-19. Port Mapping, Mnemonics, and Functions (continued)
VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
12 PM_UCA2CLK eUSCI_A2 clock input/output (direction controlled by eUSCI)
PM_UCA2RXD eUSCI_A2 UART RXD (direction controlled by eUSCI – Input)
13
PM_UCA2SOMI eUSCI_A2 SPI slave out master in (direction controlled by eUSCI)
PM_UCA2TXD eUSCI_A2 UART TXD (direction controlled by eUSCI – Output)
14
PM_ UCA2SIMO eUSCI_A2 SPI slave in master out (direction controlled by eUSCI)
15 PM_UCB2STE eUSCI_B2 SPI slave transmit enable (direction controlled by eUSCI)
16 PM_UCB2CLK eUSCI_B2 clock input/output (direction controlled by eUSCI)
PM_UCB2SDA eUSCI_B2 I
2
C data (open drain and direction controlled by eUSCI)
17
PM_UCB2SIMO eUSCI_B2 SPI slave in master out (direction controlled by eUSCI)
PM_UCB2SCL eUSCI_B2 I
2
C clock (open drain and direction controlled by eUSCI)
18
PM_UCB2SOMI eUSCI_B2 SPI slave out master in (direction controlled by eUSCI)
19 PM_TA0.0 TA0 CCR0 capture input CCI0A TA0 CCR0 compare output Out0
20 PM_TA0.1 TA0 CCR1 capture input CCI1A TA0 CCR1 compare output Out1
21 PM_TA0.2 TA0 CCR2 capture input CCI2A TA0 CCR2 compare output Out2
22 PM_TA0.3 TA0 CCR3 capture input CCI3A TA0 CCR3 compare output Out3
23 PM_TA0.4 TA0 CCR4 capture input CCI4A TA0 CCR4 compare output Out4
24 PM_TA1.1 TA1 CCR1 capture input CCI1A TA1 CCR1 compare output Out1
25 PM_TA1.2 TA1 CCR2 capture input CCI2A TA1 CCR2 compare output Out2
26 PM_TA1.3 TA1 CCR3 capture input CCI3A TA1 CCR3 compare output Out3
27 PM_TA1.4 TA1 CCR4 capture input CCI4A TA1 CCR4 compare output Out4
PM_TA0CLK Timer_A0 external clock input None
28
PM_C0OUT None Comparator-E0 output
PM_TA1CLK Timer_A1 external clock input None
29
PM_C1OUT None Comparator-E1 output
PM_DMAE0 DMAE0 input None
30
PM_SMCLK None SMCLK
Disables the output driver as well as the input Schmitt-trigger to prevent parasitic cross
31 (0FFh)
(1)
PM_ANALOG
currents when applying analog signals.
(1) The value of the PM_ANALOG mnemonic is set to 31. The port mapping registers are 5 bits wide, and the upper bits are ignored, which
results in a read value of 31.
Table 6-20. Default Mapping
PIN NAME PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
P2.0/PM_UCA1STE PM_UCA1STE eUSCI_A1 SPI slave transmit enable (direction controlled by eUSCI)
P2.1/PM_UCA1CLK PM_UCA1CLK eUSCI_A1 clock input/output (direction controlled by eUSCI)
P2.2/PM_UCA1RXD/ PM_UCA1RXD/ eUSCI_A1 UART RXD (direction controlled by eUSCI – Input)
PM_UCA1SOMI PM_UCA1SOMI eUSCI_A1 SPI slave out master in (direction controlled by eUSCI)
P2.3/PM_UCA1TXD/ PM_UCA1TXD/ eUSCI_A1 UART TXD (direction controlled by eUSCI – output)/
PM_UCA1SIMO PM_UCA1SIMO eUSCI_A1 SPI slave in master out (direction controlled by eUSCI)
P2.4/PM_TA0.1
(1)
PM_TA0.1 TA0 CCR1 capture input CCI1A TA0 CCR1 compare output Out1
P2.5/PM_TA0.2
(1)
PM_TA0.2 TA0 CCR2 capture input CCI2A TA0 CCR2 compare output Out2
P2.6/PM_TA0.3
(1)
PM_TA0.3 TA0 CCR3 capture input CCI3A TA0 CCR3 compare output Out3
P2.7/PM_TA0.4
(1)
PM_TA0.4 TA0 CCR4 capture input CCI4A TA0 CCR4 compare output Out4
P3.0/PM_UCA2STE PM_UCA2STE eUSCI_A2 SPI slave transmit enable (direction controlled by eUSCI)
P3.1/PM_UCA2CLK PM_UCA2CLK eUSCI_A2 clock input/output (direction controlled by eUSCI)
P3.2/PM_UCA2RXD/ PM_UCA2RXD/ eUSCI_A2 UART RXD (direction controlled by eUSCI – input)/
PM_UCA2SOMI PM_UCA2SOMI eUSCI_A2 SPI slave out master in (direction controlled by eUSCI)
(1) Not available on the 64-pin RGC package.
Copyright © 2015, Texas Instruments Incorporated Detailed Description 89
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