Datasheet

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MSP432P401R, MSP432P401M
SLAS826 –MARCH 2015 www.ti.com
NOTE
The glitch filter is implemented on the following digital I/Os on MSP432P401x devices: P1.0,
P1.4, P1.5, P3.0, P3.4, P3.5, P6.6, P6.7.
6.8.1.1.1 Digital I/O Glitch Filter Control Register [Address = E004_0030h]
Figure 6-14. SYS_DIO_GLTFLT_CTL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved GLTFL
T_EN
r r r r r r r r r r r r r r r rw-1
Table 6-18. SYS_DIO_GLTFLT_CTL Register Description
BIT FIELD TYPE RESET DESCRIPTION
31-1 Reserved R 0h Reserved. Always reads 0h.
0 GLTFLT_EN RW 1h
0b = Disables glitch filter on the digital I/Os.
1b = Enables glitch filter on the digital I/Os.
6.8.2 Port Mapping Controller (PMAPCTL)
The port mapping controller allows flexible and reconfigurable mapping of digital functions.
6.8.2.1 Port Mapping Definitions
The port mapping controller on MSP432P401x devices allows reconfigurable mapping of digital functions
over ports P2, P3, and P7.
Table 6-19. Port Mapping, Mnemonics, and Functions
VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
0 PM_NONE None DVSS
1 PM_UCA0CLK eUSCI_A0 clock input/output (direction controlled by eUSCI)
PM_UCA0RXD eUSCI_A0 UART RXD (direction controlled by eUSCI – Input)
2
PM_UCA0SOMI eUSCI_A0 SPI slave out master in (direction controlled by eUSCI)
PM_UCA0TXD eUSCI_A0 UART TXD (direction controlled by eUSCI – Output)
3
PM_UCA0SIMO eUSCI_A0 SPI slave in master out (direction controlled by eUSCI)
4 PM_UCB0CLK eUSCI_B0 clock input/output (direction controlled by eUSCI)
PM_UCB0SDA eUSCI_B0 I
2
C data (open drain and direction controlled by eUSCI)
5
PM_UCB0SIMO eUSCI_B0 SPI slave in master out (direction controlled by eUSCI)
PM_UCB0SCL eUSCI_B0 I
2
C clock (open drain and direction controlled by eUSCI)
6
PM_UCB0SOMI eUSCI_B0 SPI slave out master in (direction controlled by eUSCI)
7 PM_UCA1STE eUSCI_A1 SPI slave transmit enable (direction controlled by eUSCI)
8 PM_UCA1CLK eUSCI_A1 clock input/output (direction controlled by eUSCI)
PM_UCA1RXD eUSCI_A1 UART RXD (direction controlled by eUSCI – Input)
9
PM_UCA1SOMI eUSCI_A1 SPI slave out master in (direction controlled by eUSCI)
PM_UCA1TXD eUSCI_A1 UART TXD (direction controlled by eUSCI – Output)
10
PM_UCA1SIMO eUSCI_A1 SPI slave in master out (direction controlled by eUSCI)
11 PM_UCA2STE eUSCI_A2 SPI slave transmit enable (direction controlled by eUSCI)
88 Detailed Description Copyright © 2015, Texas Instruments Incorporated
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