Datasheet

PRODUCTPREVIEW
MSP432P401R, MSP432P401M
www.ti.com SLAS826 –MARCH 2015
Table 6-12. NVIC Interrupts (continued)
NVIC INTERRUPT INPUT SOURCE FLAGS IN SOURCE
INTISR[31] DMA_INT3 DMA completion interrupt3
INTISR[32] DMA_INT2 DMA completion interrupt2
INTISR[33] DMA_INT1 DMA completion interrupt1
INTISR[34] DMA_INT0
(3)
DMA completion interrupt0
INTISR[35] I/O Port P1 P1IFG.x (x = 0 through 7)
INTISR[36] I/O Port P2 P2IFG.x (x = 0 through 7)
INTISR[37] I/O Port P3 P3IFG.x (x = 0 through 7)
INTISR[38] I/O Port P4 P4IFG.x (x = 0 through 7)
INTISR[39] I/O Port P5 P5IFG.x (x = 0 through 7)
INTISR[40] I/O Port P6 P6IFG.x (x = 0 through 7)
INTISR[41] Reserved
INTISR[42] Reserved
INTISR[43] Reserved
INTISR[44] Reserved
INTISR[45] Reserved
INTISR[46] Reserved
INTISR[47] Reserved
INTISR[48] Reserved
INTISR[49] Reserved
INTISR[50] Reserved
INTISR[51] Reserved
INTISR[52] Reserved
INTISR[53] Reserved
INTISR[54] Reserved
INTISR[55] Reserved
INTISR[56] Reserved
INTISR[57] Reserved
INTISR[58] Reserved
INTISR[59] Reserved
INTISR[60] Reserved
INTISR[61] Reserved
INTISR[62] Reserved
INTISR[63] Reserved
(3) DMA_INT0 has a different functionality from DMA_INT1/2/3. Refer to Section 6.4.2 for more details.
NOTE
The Interrupt Service Routine (ISR) must ensure that the relevant interrupt flag in the source
peripheral is cleared before returning from the ISR. If this is not done, the same interrupt
may get incorrectly pended again as a new event, even though the event has already been
processed by the ISR. As there may be a few cycles of delay between the execution of the
write command and the actual write reflecting in the peripheral's interrupt flag register, the
recommendation is to carry out the write and wait for a few cycles before exiting the ISR.
Alternatively, the application can do an explicit read to ensure that the flag was cleared
before exiting the ISR.
Copyright © 2015, Texas Instruments Incorporated Detailed Description 81
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